 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| md400183/a 1 84225 features n single chip 100basetx/100basefx/10baset physical layer solution n four independent channels in one ic n 3.3v power supply with 5v tolerant i/o n dual speed - 10/100 mbps n half and full duplex n mii interface or reduced pin count mii (rmii) interface to ethernet controller n mi interface for con?uration and status n optional repeater interface n autonegotiation for 10/100, full/half duplex hardware controlled advertisement n meets all applicable ieee 802.3, 10baset, 100basetx and 100basefx standards n on chip wave shaping - no external filters required n adaptive equalizer for 100basetx n baseline wander correction n led outputs link activity collision full duplex far end fault (for fx) 10/100 n 160l pqfp description the 84225 is a highly integrated ethernet transceiver for twisted pair and ?er ethernet applications. the 84225 can be con?ured for either 100 mbps (100basefx or 100basetx) or 10 mbps (10baset) ethernet operation. the 84225 consists of four (4) separate and independent channels. each channel consists of: 4b5b/manchester encoder, scrambler, transmitter with wave shaping and on- chip ?ters, transmit output driver, receiver with adaptive equalizer, ?ters, baseline wander correction, clock and data recovery, descrambler, 4b5b/manchester decoder, and controller interface (mii or rmii). the addition of internal output waveshaping circuitry and on-chip ?ters eliminates the need for external ?ters normally required in 100basetx and 10baset applications. the 84225 can automatically con?ure itself for 100 or 10 mbps and full or half duplex operation, for each channel independently, using the on-chip autonegotiation algorithm. the 84225 can access eleven 16-bit registers for each channel through the management interface (mi) serial port. these registers comply to clause 22 of ieee 802.3u and contain con?uration inputs, status outputs, and device capabilities. the 84225 is ideal as a media interface for 100basetx/ 100basefx/10baset switching hubs, repeaters, routers, bridges, and other multi port applications. the 84225 is implemented in a low power cmos technology and operates with a 3.3v power supply. 84225 99061 quad 100basetx/fx/10baset physical layer device note: check for latest data sheet revision before starting any designs. seeq data sheets are now on the web, at www.lsilogic.com this document is an lsi logic document. any reference to seeq technology should be consid- ered lsi logic.
2 md400183/a 84225 1.0 pin con?uration 84225 top view 160 pin pqfp 2 1 3 7 6 5 4 8 9 gnd 13 12 11 10 14 16 15 vdd ad_rev 26 25 24 23 22 21 20 19 18 17 36 35 34 33 32 31 30 29 28 27 40 39 38 37 led0_3 led1_3 led2_3 led0_2 led1_2 led2_2 led0_1 led1_1 led2_1 led0_0 led1_0 led2_0 gnd vdd phyad2 phyad3 phyad4 gnd vdd rxd3_0 rxd0_0 rxd1_0 rxd2_0 rxdv_0 rxclk_0 rxer_0/rxd4_0 txer_0/txd4_0 txclk_0 txclk_0 txen_0 txen_0 txd1_0 txd0_0 txd2_0 txd3_0 col_0 vdd gnd crs_0 42 41 43 47 46 45 44 48 49 rxclk_1 53 52 51 50 54 56 55 col_1 66 65 64 63 62 61 60 59 58 57 76 75 74 73 72 71 70 69 68 67 80 79 78 77 vdd rxd3_1 rxer_1/rxd4_1 txclk_1 gnd crs_1 gnd vdd rxd3_2 rxd0_2 rxd1_2 rxd2_2 rxdv_2 rxclk_2 rxer_2/rxd4_2 txer_2/txd4_2 txclk_2 txen_2 txd1_2 txd0_2 txd2_2 txd3_2 col_2 vdd gnd crs_2 rxdv_1 rxd0_1 rxd1_1 rxd2_1 txer_1/txd4_1 txd2_1 txd1_1 txd0_1 txen_1 txd3_1 rxd3_3 rxd2_3 119 120 118 114 115 116 117 113 112 108 109 110 111 107 105 106 95 96 97 98 99 100 101 102 103 104 85 86 87 88 89 90 91 92 93 94 81 82 83 84 speed_3 speed_2 led3_3 led3_2 led3_1 led3_0 speed_1 speed_0 aneg leddef dplx_3 repeater mdio col_3 gnd vdd txclk_3 rxd1_3 rxclk_3 rxdv_3 rxd0_3 rxer_3/rxd4_3 txer_3/txd4_3 txen_3 txd3_3 txd2_3 txd1_3 txd0_3 crs_3 regdef mdc vdd rmii_en dplx_0 dplx_1 dplx_2 vdd gnd reset clkin 159 160 158 154 155 156 157 153 152 148 149 150 151 147 145 146 135 136 137 138 139 140 141 142 143 144 125 126 127 128 129 130 131 132 133 134 121 122 123 124 gnd vdd gnd gnd tpip_3/fxop_3 tpin_3/fxon_3 rext vdd tpop_3/fxin_3 gnd vdd tpon_3/fxip_3 sd_3/fxen_3 gnd vdd tpon_2/fxip_2 tpop_2/fxin_2 sd_2/fxen_2 tpin_2/fxon_2 tpip_2/fxop_2 tpip_1/fxop_1 tpin_1/fxon_1 vdd gnd vdd gnd vdd gnd tpop_1/fxin_1 sd_1/fxen_1 tpon_1/fxip_1 tpon_0/fxip_0 gnd vdd tpop_0/fxin_0 gnd sd_thr tpin_0/fxon_0 tpip_0/fxop_0 sd_0/fxen_0 84225 160 pin pqfp top view md400183/a 3 84225 1.0 pin description power supplies pin # pin name i/o description 15 16 22 40 41 60 78 96 100 107 125 128 132 135 144 147 151 154 vdd --- positive supply. +3.3 +/-5% volts. 7 14 21 39 56 59 77 95 108 121 122 127 131 134 141 146 150 153 160 gnd --- ground. 0 volts. 4 md400183/a 84225 1.0 pin description (cont d) media interface pin # pin name i/o description 126 136 145 155 tpop_[3:0]/ fxin_[3:0] i/o twisted pair transmit output, positive. fiber receive input, negative. 129 133 148 152 tpon_[3:0]/ fxip_[3:0] i/o twisted pair transmit output, negative. fiber receive input, positive. 123 139 142 158 tpip_[3:0]/ fxop_[3:0] i/o twisted pair receive input, positive. fiber transmit output, positive. 124 138 143 157 tpin_[3:0]/ fxon_[3:0] i/o twisted pair receive input, negative. fiber transmit output, negative. 130 137 149 156 sd_[3:0]/ fxen_[3:0] i fiber interface signal detect input. fiber interface enable. when this pin in not tied to gnd, the ?er interface is enabled and this pin becomes a signal detect ecl input. the trip point for this ecl input is determined by the voltage applied to the sd_thr pin. when this pin is tied to gnd, the ?er interface is disabled (i.e. tp interface is enabled). 159 sd_thr --- fiber interface signal detect threshold reference. the voltage applied to this pin sets the reference level for the ?er interface sd input pin so that the device can directly connect sd pin to both 3.3v and 5v ?er optic tansceivers. typically, this pin is either tied to gnd (for 3.3v) or to an external voltage divider (for 5v). 140 rext --- transmit current set. an external resistor connected between this pin and gnd will set the level for the transmit outputs. md400183/a 5 84225 1.0 pin description (cont d) controller interface (mii & rmii) pin # pin name i/o description 87 69 50 31 txclk_[3:0] o transmit clock output. these interface outputs provide clocks to external controllers. transmit data from the controller on txd, txen, and txer is clocked in on the rising edges of txclk and clkin. 88 70 51 32 txen_[3:0] i transmit enable input. these interface inputs must be be asserted active high to allow data on txd and txer to be clocked in on the rising edges of txclk and clkin. [92:89] [74:71] [55:52] [36:33] txd[3:0]_3 txd[3:0]_2 txd[3:0]_1 txd[3:0]_0 i transmit data input. these interface inputs contain input nibble data to be transmitted on the tp or fx outputs and are clocked in on rising edges of txclk and clkin. in rmii mode, only txd[1:0] are used. 86 68 49 30 txer_[3:0]/ txd4_[3:0] i transmit error input. these interface inputs initiate an error pattern to be transmitted on the tp or fx outputs and are clocked in on rising edges of txclk when txen is asserted. if the channel is placed in the bypass 4b5b encoder mode, these pins are recon?ured to be the ?th txd transmit data input, txd4. in rmii mode, these pins are not used. 84 66 47 28 rxclk_[3:0] o receive clock output. these interface outputs provide a clock to the controller. receive data on rxd, rxdv, and rxer is clocked out to the controller on falling edges of rxclk. 94 76 58 38 crs_[3:0] o carrier sense output. these interface outputs are asserted active high when valid data is detected on the receive tp or fx inputs and is clocked out on the falling edge of rxclk. 83 65 46 27 rxdv_[3:0] o receive data valid output. these interface outputs are asserted active high when valid decoded data is present on the rxd outputs and is clocked out on falling edges of rxclk. in rmii mode, these pins are not used. [79:82] [61:64] [42:45] [23:26] rxd[3:0]_3 rxd[3:0]_2 rxd[3:0]_1 rxd[3:0]_0 o receive data output. these interface outputs contain recovered nibble data from the tp or fx inputs and are clocked out on the falling edges of rxclk. in rmii mode, only rxd[1:0] are used. 85 67 48 29 rxer_[3:0]/ rxd4_[3:0] o receive error output. these interface outputs are asserted active high when coding or other speci?d errors are detected on the tp or fx inputs and are clocked out on falling edges of rxclk. if the channel is placed in the bypass 4b5b decoder mode, these pins are recon?ured to be the ?th rxd receive data output, rxd4. 93 75 57 37 col_[3:0] o collision output. these interface outputs are asserted active high when collision between transmit and receive data is detected. 6 md400183/a 84225 1.0 pin description (cont d) management interface (mi) pin # pin name i/o description 99 mdc i management interface (mi) clock input. this mi clock shifts serial data into and out of mdio on rising edges. 97 mdio i/o management interface (mi) data input/output. this bidirectional pin contains serial data that is clocked in and out on rising edges of the mdc clock. 98 regdef i pullup invalid register read select this active low input controls the default values that are read from invalid (unused) register locations. 1 = all unused register locations will return a value of ?000 when read. 0 = all unused register locations will return a value of ?fff when read. note: not available on rev. b product. on rev. b product all invalid register locations return a value of ?000 when read. 20 19 18 phyad[4:2] i mi physical device address input. these pins set the three most signi?ant bits of the phy address. the two least signi?ant bits of the phy address are set internally to match the channel number, as shown below: phyad1 phyad0 channel 3 1 1 channel 2 1 0 channel 1 0 1 channel 0 0 0 md400183/a 7 84225 1.0 pin description (cont d) led pin # pin name i/o description 117 116 115 114 led3_[3:0] o led output. the default functions of these pins are 100 mbps link detect outputs assuming leddef = 0. these pins can drive an led from both vdd and gnd. please refer to table 1a. for led description 3 6 10 13 led2_[3:0] o led output. the default functions of these pins are activity detect outputs assuming leddef = 0. these pins can drive an led from both vdd and gnd. please refer to table 1a. for led description 2 5 9 12 led1_[3:0] o led output. the default functions of these pins are full duplex detect outputs assuming leddef = 0. these pins can drive an led from both vdd and gnd. please refer to table 1a. for led description 1 4 8 11 led0_[3:0] o led output. the default functions of these pins are 10 mbps link detect outputs assuming leddef = 0. these pins can drive an led from both vdd and gnd. please refer to table 1a. for led description 110 leddef i led default select input. this pin changes the default selection for the led s in the mi serial port global con?uration register. 1 = link + act, col, fdx, 10/100 0 = link100, act, fdx, lnk10 drivers 8 md400183/a 84225 1.0 pin description (cont d) miscellaneous pin # pin name i/o description 111 aneg i autonegotiation enable input. this digital input, anded with register bit 0.12, enables autonegotiation for all channels. 1 = autonegotiation on & combined with speed and duplex pins, control advertisement. please refer to table 1 for the different combinations. 0 = off 120 119 113 112 speed_[3:0] i speed selection input. these digital inputs, anded with register bit 0.13, select speed in each corresponding channel. please refer to table 1 for the different combinations. 1 = 100 mbps mode 0 = 10 mbps mode 103 104 105 106 dplx_[3:0] i duplex selection input. these digital inputs, ored with register bit 0.8, select the duplex mode in each corresponding channel. they control advertisement when aneg is enabled. please refer to table 1 for the different combinations. 1 = full duplex mode 0 = half duplex mode 102 repeater i repeater mode enable input. this digital input, ored with register bit 17.14, enables repeater mode for all channels. 1 = repeater mode enabled 0 = normal operation 101 rmii_en i reduced pin count mii interface enable. 1 = rmii mode enabled 0 = mii enabled 17 ad_rev i pullup address reverse input. 1 = normal in this mode, physical ports 0-3 are mapped to mi addresses 0-3 in the same order. 0 = reverse address mode select in this mode, physical ports 0-3 are mapped to mi addresses 3-0 respectively. this is the reverse to the normal order. md400183/a 9 84225 1.0 pin description 118 clkin i clock input. in mii mode, there must be a 25 mhz clock input to this pin. in rmii mode, there must be a 50 mhz clock input to this pin. txclk is generated from the input to this pin. 109 reset i pullup hardware reset input. 1 = normal 0 = device in reset state (reset is complete 50 ms after reset goes high). table 1. autonegotiation, speed & duplex mode combinations input pins mode selected aneg speed[3:0] duplx [3:0] auto- forced advertised neg modes capabilities [note 2] speed dplx speed dplx 0 0000 0000 off 10 half na na 0 0000 1111 off 10 full na na 0 1111 0000 off 100 half na na 0 1111 1111 off 100 full na na 1 0000 0000 on na na 10 half 1 0000 1111 on na na 10 half/full 1 1111 0000 on na na 10/100 half/full [3] 1 1111 1111 on na na 10/100 half note 1: the single aneg pin applies to all four channels. the four speed and dplx apply to each individual channel. the pins above are shown for all four channels, but each channel can be individually con?ured for speed and dplx by appropriately setting the pin for that channel. note 2: forced modes assume that registers 0 and 4 are at default values. note 3: the 84225 can be either controlled through the software or through the hardware. if the device needs to be con- trolled through the software (registers 0 to 4), then these seven pins (aneg, speed[3:0] , duplx[3:0]) have to be tied to their default values of 1, 1111, and 0000 respectively. 10 md400183/a 84225 table 1a. led de?itions as per the leddef pin name output state description led tied led tied leddef to gnd to vdd led0 [1] 0 = 100 mbps link off on leddef = 1 detected (10/100) 1 = 10 mbps link on off detected trisate = no link off off led1 0 = full duplex mode off on detect with link pass (fdx/hdx) 1 = half duplex mode on off detect with link pass tristate = no link off off led2 0 = collision detect off on (col) 1 = no collision on off led3 0 = link detect off on (link + act) blink = link detect + activity blink blink 1 = no link detect or activity on off led0 [1] 0 = 10 mbps link off on leddef = 0 detected (link10) 1 = no 10 mbps link on off detected led1 0 = full duplex mode off on detect with link pass (fdx/hdx) 1 = half duplex mode on off detect with link pass tristate = no link off off led2 blink = activity occurred off on (stretch pulse to 100 ms) (act) 1 = no activity on off led3 0 = link100 detected off on 1 = no link100 on off (link100) detected note 1. led 0 becomes fef when fx interface is enabled. 0 = fef detected 1 = no fef detected md400183/a 11 84225 txclk_3 txer_3/txd4_3 txen_3 txd[3:0]_3 controller interface col_3 rxclk_3 rxer_3/rxd4_3 rxdv_3 rxd[3:0]_3 crs_3 led drivers led3_3 collision 4b5b decoder descrambler clock & data recovery auto- negotiation & link serial port (mi) mdio clock & data recovery (manchester decoder) lp filter rom dac + 10bt transmitter clock generator manchester encoder 4b5b encoder scrambler tpop_3 current source + 100basetx transmitter clock generator tpon_3 lp filter tpip_3 tpin_3 lp filter + +/?vth + 10btx receiver mlt3 encoder figure 1. 84225 block diagram adaptive equalizer + 100btx receiver mlt3 decoder regdef mdc 100basefx transmitter 100basefx receiver sd_thr sd/fxen_3 aneg speed_[3:0] dplx_[3:0] ad_rev repeater reset global clkin rmii_en phyad[4:2] led2_3 led1_3 led0_3 squelch nrzi encoder rext per channel functions global channel 3 channel 0 channel 1 channel 2 squelch +/?vth + + + vth + nrzi decoder leddef 12 md400183/a 84225 2.0 functional description 2.1 general the 84225 is a complete 10/100 mbps ethernet media interface ic. the 84225 has four separate and independent channels. each channel has the following main sections: controller interface, encoder, decoder, scrambler, descrambler, clock and data recovery, twisted pair and ?er interface transmitter, twisted pair and ?er interface receiver, and auto negotiation. a management interface (mi) serial port, which provides access to eleven registers for each channel, is common to all four channels. figure 1 shows the 84225 block diagram. the 84225 can operate as a 100basetx or 100basefx device (100 mbps mode) or as a 10baset device (10 mbps mode). the 100 mbps and 10 mbps modes differ in data rate, signalling protocol, and allowed wiring as follows: the 100 mbps fx mode uses two ?er connections with 4b5b encoded nrzi 125 mhz binary data through an ecl-type driver to achieve a throughput of 100 mbps. the 100 mbps tx mode uses two pairs of category 5, or better, utp or stp twisted pair cable with 4b5b encoded, scrambled, and mlt3 coded (ternary) 125 mhz data to achieve a throughput of 100 mbps. ?the 10 mbps mode uses two pairs of category 3, or better, utp or stp twisted pair cable with manchester encoded 10 mhz binary data to achieve a 10 mbps thruput. the data symbol format on the ?er or twisted pair cable for the 100 and 10 mbps modes is de?ed in ieee 802.3 speci?ations and shown in figure 2. on the transmit side for 100 mbps operation, data is received on the controller interface from an external ethernet controller per the format shown in figure 3. the data is sent to the encoder for formatting. for tx operation, the encoded data is sent to the scrambler. the encoded and scrambled data is then sent to the tx transmitter. the transmitter converts the encoded and figure 2. frame format preamble sfd da llc data fcs sa interframe gap ethernet mac frame ln interframe gap ssd preamble sfd llc data fcs da idle 100 base-tx data symbols sa idle ln esd = [ 1 1 1 1 ...] = [ 0 1 1 0 1 0 0 1 1 1 ] = [ data ] = [ 1 1 ] = [ 1 0 1 0 ...] 62 bits long = [ 1 1 0 0 0 1 0 0 0 1 ] esd da, sa, ln, llc data, fcs ssd preamble sfd idle before / after 4b5b encoding, scrambling, and mlt3 coding preamble sfd llc data fcs da idle 10 base-t data symbols sa idle ln soi = [ no transitions ] = [ 1 1 ] with no mid bit transition = [ data ] = [ 1 1 ] = [ 1 0 1 0 ... ] 62 bits long soi da, sa, ln, llc data, fcs sfd preamble idle before / after manchester encoding ssd preamble sfd llc data fcs da idle 100 base-fx data symbols sa idle ln esd = [ 1 1 1 1 ...] = [ 0 1 1 0 1 0 0 1 1 1 ] = [ data ] = [ 1 1 ] = [ 1 0 1 0 ...] 62 bits long = [ 1 1 0 0 0 1 0 0 0 1 ] esd da, sa, ln, llc data, fcs ssd preamble sfd idle before / after 4b5b encoding, md400183/a 13 84225 scrambled data into mlt3 ternary format. the transmitter then preshapes the output and drives the twisted pair cable. for fx operation, the encoded data is converted to nrzi format which drives a binary (two level) signal to the ?er transceiver interface (pmd). on the receive side for 100basetx operation, the tx receiver removes any high frequency noise from the input, equalizes the input signal to compensate for the low pass effects of the cable, and quali?s the data with a squelch algorithm. the tx receiver then converts the data from mlt3 coded twisted pair levels to internal digital levels. the output of the receiver then goes to a clock and data recovery block which recovers a clock from the incoming data, uses the clock to latch in valid data into the device, and converts the data back to nrz data. the data is then unscrambled and decoded by the 4b5b decoder and descrambler, respectively, and output to an external ethernet controller by the controller interface. 100base fx receiver operation is the same as tx except there is no equalizer, descrambler, and has a seperate ecl receiver. 10 mbps operation is similar to the 100 mbps operation, except: there is no scrambler/descrambler. the encoder/decoder is manchester instead of 4b5b. the data rate is 10 mbps instead of 100 mbps. the twisted pair symbol data is two level manchester instead of ternary mlt3. the fx interface is disabled for 10 mbps operation. the autonegotiation block automatically con?ures each channel for either 100basetx or 10baset, and either full or half duplex operation. this con?uration is based on the capabilities selected for the channel and capabilities detected from the remote device connected to the channel. the management interface (the mi serial port) is a two pin bidirectional link through which con?uration inputs can be set and channel status outputs read. each block plus the operating modes are described in more detail in the following sections. since the 84225 can operate as a 100basefx, 100basetx or a 10baset device, each of the following sections describes the performance in both 100 and 10 mbps modes. 2.2 controller interface 2.2.1 general the 84225 has three interfaces to an external controller: media independent interface (mii), reduced pin mii (rmii), and five bit interface (fbi). mii is the default interface. rmii is selected by asserting the rmii_en pin, a global control (all channels effected). fbi is selected, on a per port basis, by setting the bypass encoder bit in the mi serial port channel con?uration register (register 17). 2.2.2 mii - 100 mbps the mii is a nibble wide packet data interface de?ed in ieee 802.3. the 84225 meets all mii requirements outlined in ieee 802.3. the 84225 can directly connect, without external logic, to any ethernet controller or other device that also complies with the ieee 802.3 mii speci?ation. the mii frame format is shown in figure 3. the mii consists of four transmit data bits (txd[3:0]), transmit clock (txclk), transmit enable (txen), transmit error (txer), four receive data bits (rxd[3:0]), receive clock (rxclk), carrier sense (crs), receive data valid (rxdv), receive data error (rxer), and collision (col). the transmit clock (txclk) is a common signal for all four channels. all other signals are separate for each channel. the transmit and receive clocks operate at 25 mhz in 100 mbps mode. on the transmit side, the txclk output runs continuously at 25 mhz. when no data is to be transmitted, txen must be deasserted. while txen is deasserted, txer and txd[3:0] are ignored and no data is clocked into the device. when txen is asserted on the rising edge of txclk, data on txd[3:0] is clocked into the device on rising edges of the txclk output clock. txd[3:0] input data is nibble wide packet data whose format is speci?d in ieee 802.3 and shown in figure 3. when all packet data has been latched into the device, txen must be deasserted on the rising edge of txclk. txer is also clocked in on rising edges of the txclk clock. txer is a transmit error signal which, when asserted, will substitute an error nibble in place of the 14 md400183/a 84225 1. 1st preamble nibble received. depending on mode, device may eliminate either all or some of the preamble nibbles, up to 1st sfd nibble. 2. 1st sfd nibble received. 3. 1st data nibble received. 4. d0 through d7 are the first 8 bits of the data field. signals bit value rxd0 x x 1 1 1111111111111 1 2 1 d0 3 d4 4 rxd1 x x 0000000000000000d1d5 rxd2 x x 1111111111111111d2d6 rxd3 x x 0000000000000001d3d7 rxdv 0011111111111111111 1 1. 1st preamble nibble transmitted. 2. 1st sfd nibbletransmitted. 3. 1st data nibble transmitted. 4. d0 through d7 are the first 8 bits of the data field. signals bit value txd0 x x 1 1 1111111111111 1 2 1 d0 3 d4 4 txd1 x x 0000000000000000d1d5 txd2 x x 1111111111111111d2d6 txd3 x x 0000000000000001d3d7 txen 0011111111111111111 1 data 1 prmble preamble = [ 1 0 1 0 ... ] 62 bits long] sfd = [ 1 1 ] datan = [between 64-1518 data bytes] idle = txen = 0 start of frame 2 bits data 2 data n -1 data n idle idle preamble data nibbles 62 bits txen = 0 txen = 0 txen = 1 a.) mii frame format sfd d6 d7 d4 d5 d2 d3 d0 d1 lsb msb mac? serial bit stream first bit first nibble second nibble mii nibble stream txd1 / rxd1 txd0 / rxd0 txd3 / rxd3 txd2 / rxd2 b.) mii nibble order c.) transmit preamble and sfd bits d.) receive preamble and sfd bits figure 3. mii frame format md400183/a 15 84225 normal data nibble that was clocked in on the txd[3:0] nibble at the same time as the txer assertion. the error nibble is the /h/ symbol, as de?ed in ieee 802.3 and shown in ?able 1. 4b/5b symbol mapping,? since clkin (input clock) generates txclk (output clock), txd[3:0], txen, and txer are also clocked in on the rising edges of clkin. on the receive side, as long as a valid data packet is not detected, crs and rxdv are deasserted and rxd[3:0] is held low. when the start of packet is detected, crs is asserted on the falling edge of rxclk. the assertion of rxdv indicates that valid data is available on rxd[3:0]. data may be externally latched using the rising edge of rxclk. the rxd[3:0] data has the same frame structure as the txd[3:0] data, speci?d in ieee 802.3 and shown in figure 3. when the end of packet is detected, crs and rxdv are deasserted, and rxd[3:0] is held low. crs and rxdv also stay deasserted if the channel is in link fail state. rxer is a receive error output that is asserted when certain errors are detected on a data nibble. rxer is asserted on the falling edge of rxclk for the duration of the rxclk clock cycle during which the nibble containing the error is output on rxd[3:0]. the collision output, col, is asserted whenever the collision condition is detected. 2.2.3 mii - 10mbps 10 mbps operation is identical to the 100 mbps operation, except: txclk and rxclk clock frequency is 2.5 mhz. txer is ignored. rxer is disabled and always held low. receive operation is modi?d as follows. on the receive side, when the squelch circuit determines that invalid data is present on the tp (twisted pair) inputs, the receiver is idle. during idle, rxclk follows txclk, rxd[3:0] is held low, and crs and rxdv are deasserted. when a start of packet is detected on the tp receive inputs, crs is asserted and the clock recovery process starts on the incoming tp input data. after the receive clock has been recovered from the data, the rxclk is switched over to the recovered clock output and the data valid signal rxdv is asserted on a falling edge of rxclk. once rxdv is asserted, valid data is clocked out on rxd[3:0] on falling edges of the rxclk clock. the rxd[3:0] data has the same packet structure as the txd[3:0] data and is formatted as speci?d in ieee 802.3 and shown in figure 3. when the end of packet is detected, crs and rxdv are deasserted. crs and rxdv also stay deasserted as long as the channel is in the link fail state. 2.2.4 rmii - 100 mbps the rmii is a reduced pin count version of the mii de?ed by an industry group, the rmii consortium. the rmii is a two-bit wide packet data interface that operates at 50 mhz. the 84225 meets all the rmii requirements outlined in the rmii consortium speci?ations and can directly connect to any ethernet controller that also complies with the rmii speci?ations. the rmii is similar to the mii, except: the data path is two bits wide instead of four. transmit and receive data is passed over txd[1:0] and rxd[1:0] pins, respectively. the clkin clock frequency must be 50 mhz instead of 25 mhz. ? all timing for both transmit and receive is referenced to a single clock on clkin instead of txclk for transmit and rxclk for receive. ?an elastic buffer is present in the receive data path to account for any difference between the clkin and receive data frequencies. the elastic buffer is 32 bits in length. input data from the receiver ?ls the buffer to a predetermined threshold level before data is passed to the rmii outputs. this threshold level can be con?ured to either 4 bits or 16 bits by appropriately setting the rmii threshold select bit in the mi serial port global con?uration register. ?the mii rxdv and crs inputs are combined into one signal that is outputted on the crs pin. crs is asserted active high when incoming packet data is detected on the receive inputs, stays asserted high until packet data is no longer detected, and toggles at a 25 mhz rate (low for ?st di-bit of mii nibble, high for second, etc.) from the end of the packet data detection until end of valid data transfer from the elastic buffer. during this toggling interval, valid data is still being output on rxd[1:0]. crs is ?ally deasserted when all data has been output from the internal elastic buffer on rxd[1:0]. ? rxd[1:0]=00 from start of crs until valid data is ready to be output. ? txen to crs loopback is disabled. ? any packet that contains an error will assert rxer and substitute rxd[1:0]=10 for all the data bits from the error detect point until the end of packet. 16 md400183/a 84225 2.2.5 rmii - 10 mbps 10 mbps rmii operation is identical to 100 mbps rmii operation, except: the clkin frequency remains at 50 mhz (same as 100 mbps operation). each data di-bit must be input on txd[1:0] for ten consecutive clkin cycles. each data di-bit will be output on rxd[1:0] for ten consecutive clkin cycles. 2.2.6 fbi - 100 mbps the five bit interface (fbi), or symbol interface, is a ?e bit wide interface produced when the 4b5b encoder/ decoder is bypassed. the fbi is primarily used for repeaters or ethernet controllers that have integrated encoder/decoders. the fbi is identical to the mii, except: the fbi data path is ?e bits wide, not nibble wide like the mii. txer pin is changed to be the ?th transmit data bit, txd4. rxer pin is changed to be the ?th receive data bit, rxd4. crs is asserted as long as the device is in the link pass state (crs no longer asserted/deasserted at beginning/end of packet). col is not valid. rxdv is not valid. txen is ignored. 2.2.7 fbi - 10 mbps the fbi is not available in 10 mbps mode. 2.2.8 selection of mii, rmii, or fbi mii is the default interface to the mac controller. rmii is selected by asserting the rmii_en pin, a global control. the fbi is automatically enabled when the 4b5b encoder/ decoder is bypassed. bypassing the encoder/decoder passes the 5b symbols between the receiver/transmitter directly to the fbi without any alteration or substitutions. the 4b5b encoder/decoder can be bypassed by setting the bypass encoder bit in the mi serial port channel con?uration register. when the fbi is enabled, it may also be desirable to bypass the scrambler/descrambler and disable the internal crs loopback function. the scrambler/ descrambler can be bypassed by setting the bypass scrambler bit in the mi serial port channel con?uration register. the internal crs loopback can be disabled by setting the txen to crs loopback disable bit in the mi serial port channel con?uration register. 2.2.9 mii disable the mii and fbi inputs and outputs can be disabled by setting the mii disable bit in the mi serial port control register. when the mii is disabled, the inputs are ignored, the outputs are placed in high impedance state, and the tp output is high impedance. 2.2.10 txen to crs loopback disable the internal txen to crs loopback can be disabled by appropriately setting the txen to crs loopback disable bit in the mi serial port channel con?uration register. txen to crs loopback is disabled in rmii mode. 2.3 encoder 2.3.1 4b5b encoder - 100 mbps 100basetx and 100basefx require that the data be 4b5b encoded. 4b5b coding converts the 4 bit data nibbles into 5 bit data words. the mapping of the 4b nibbles to the 5b code words is speci?d in ieee 802.3 and shown in table 2. the 4b5b encoder on the 84225 takes 4b nibbles from the controller interface, converts them into 5b words according to, table 2, and sends the 5b words to the scrambler. the 4b5b encoder also substitutes the ?st eight bits of the preamble with the ssd delimiters (/j/k/ symbols) and adds an esd delimiter (/t/r/ symbols) to the end of each packet, as de?ed in ieee 802.3 and shown in figure 2. the 4b5b encoder also ?ls the period between packets, called the idle period, with a continuous stream of idle symbols, as shown in figure 2. md400183/a 17 84225 table 2. 4b/5b symbol mapping * these 5b codes are not used. for decoder, these 5b codes are decoded to 4b 0000. for encoder, 4b 0000 is encoded to 5b 11110, as shown in symbol 0. 2.3.2 manchester encoder - 10 mbps the manchester encoding process combines clock and nrz data such that the ?st half of the data bit contains the complement of the data, and the second half of the data bit contains the true data, as speci?d in ieee 802.3. this guarantees that a transition always occurs in the middle of the bit cell. the 84225 manchester encoder converts the 10 mbps nrz data from the controller interface into a single data stream for the tp transmitter and adds a start of idle pulse (soi) at the end of the packet as speci?d in ieee 802.3 and shown in figure 2. the manchester encoding process is only done on actual packet data, and the idle period between packets is not manchester encoded, but ?led with link pulses. symbol name description 5b code 4b code 0 data 0 11110 0000 1 data 1 01001 0001 2 data 2 10100 0010 3 data 3 10101 0011 4 data 4 01010 0100 5 data 5 01011 0101 6 data 6 01110 0110 7 data 7 01111 0111 8 data 8 10010 1000 9 data 9 10011 1001 a data a 10110 1010 b data b 10111 1011 c data c 11010 1100 d data d 11011 1101 e data e 11100 1110 f data f 11101 1111 i idle 11111 0000 j ssd #1 11000 0101 k ssd #2 10001 0101 t esd #1 01101 0000 r esd #2 00111 0000 h halt 00100 unde?ed --- invalid codes all others* 0000* 2.3.3 encoder bypass the 4b5b encoder can be bypassed by setting the bypass encoder/decoder bit in the mi serial port channel con?uration register. when this bit is set to bypass the encoder/decoder, 5b code words are passed directly from the controller interface to the scrambler without any alterations. setting this bit automatically places the device in the fbi mode as described in the controller interface section. 2.4 decoder 2.4.1 4b5b decoder - 100 mbps since the fx or tx input data is 4b5b encoded on the transmit side, it must also be decoded by the 4b5b decoder on the receive side. the mapping of the 5b nibbles to the 4b code words is speci?d in ieee 802.3 and shown in table 2. the 84225 4b5b decoder takes the 5b code words from the descrambler, converts them into 4b nibbles per table 2, and sends the 4b nibbles to the controller interface. the 4b5b decoder also strips off the ssd delimiter (/j/k/ symbols) and replaces them with two 4b data 5 nibbles (/5/ symbol), and strips off the esd delimiter (/t/r/ symbols) and replaces it with two 4b data 0 nibbles (/i/ symbol), per ieee 802.3 speci?ations and shown in figure 2. the 4b5b decoder detects ssd, esd and, codeword errors in the incoming data stream as speci?d in ieee 802.3. these errors are indicated by asserting rxer output while the errors are being transmitted across rxd[3:0], and they are also indicated by setting ssd, esd, and codeword error bits in the mi serial port channel status output register. 2.4.2 manchester decoder - 10 mbps in manchester coded data, the ?st half of the data bit contains the complement of the data, and the second half of the data bit contains the true data. the 84225 manchester decoder converts the single data stream from the tp receiver into nrz data for the controller interface by decoding the data and stripping off the soi pulse. since the clock and data recovery block has already separated the clock and data from the tp receiver, the manchester decoding process to nrz data is inherently performed by that block. 18 md400183/a 84225 2.4.3 decoder bypass the 4b5b decoder can be bypassed by setting the bypass encoder/decoder bit in the mi serial port channel con?uration register. when this bit is set to bypass the encoder/decoder: 5b code words are passed directly to the controller interface from the descrambler without any alterations. crs is asserted whenever the device is in the link pass state. 2.5 clock and data recovery 2.5.1 clock recovery - 100 mbps clock recovery is done with a pll. if there is no valid data present on the receive inputs, the pll is locked to the 25 mhz txclk. when valid data is detected on the receive inputs with the squelch circuit and when the adaptive equalizer has settled, the pll input is switched to the incoming data stream. the pll then recovers a clock by locking onto the transitions of the incoming signal. the recovered clock frequency is a 25 mhz nibble clock, and that clock is output as the controller interface signal rxclk. for fx operation, when the sd pin is asserted, the pll input is switched to the incoming data on the input. 2.5.2 data recovery - 100 mbps data recovery is performed by latching in data from the receive inputs with the recovered clock extracted by the pll. the data is then converted from a single bit stream into a nibble widedone by latching in valid data from the receiver with the recovered clock extracted by the pll. the data is then converted from a single bit stream into a nibble wide data word. 2.5.3 clock recovery - 10 mbps the clock recovery process for 10 mbps mode is identical to the 100 mbps mode, except: the recovered clock frequency is a 2.5 mhz nibble clock. the pll is switched from txclk to the tp input when the squelch indicates valid data. the pll locks onto the preamble signal in less than 12 transitions (bit times). some of the preamble data symbols are lost while the pll is locking onto the preamble, however, the data receiver block recovers enough preamble symbols to pass at least 6 nibbles of preamble to the controller interface as shown in figure 3. 2.5.4 data recovery the data recovery process for 10 mbps mode is identical to the 100 mbps mode, except, the recovered clock frequency is a 2.5 mhz nibble clock. as mentioned in the manchester decoder section, the data recovery process inherently performs decoding of manchester encoded data from the tp inputs. 2.6 scrambler 2.6.1 100 mbps 100basetx requires scrambling to reduce the radiated emmisions on the twisted pair. the 84225 scrambler takes the encoded data from the 4b5b encoder, scrambles it per the ieee 802.3 speci?ations, and sends it to the tp transmitter. the scrambler circuitry of the 84225 is designed so that none of the individual scrambler sections on-chip will be synchronous with the others to minimize emi issues. 2.6.2 10 mbps a scrambler is not used in 10 mbps mode. 2.6.3 scrambler bypass the scrambler can be bypassed by setting the bypass scrambler/descrambler bit in the mi serial port channel con?uration register. when this bit is set, the 5b data bypasses the scrambler and goes directly from the 4b5b encoder to the twisted pair transmitter. 2.7 descrambler 2.7.1 100 mbps the 84225 descrambler takes the scrambled data from the data recovery block, descrambles it per the ieee 802.3 speci?ations, aligns the data on the correct 5b word boundaries, and sends it to the 4b5b decoder. the algorithm for synchronization of the descrambler is the same as the algorithm outlined in the ieee 802.3 speci?ation. once the descrambler is synchronized, it will maintain synchronization as long as enough descrambled idle pattern 1 s are detected within a given interval. to stay in synchronization, the descrambler needs to detect at least 25 consecutive descrambled idle pattern 1 s in a 1 ms interval. if 25 consecutive descrambled idle pattern 1 s are not detected within the 1 ms interval, the descrambler goes out of synchronization and restarts the synchronization process. md400183/a 19 84225 if the descrambler is in the unsynchronized state, the descrambler loss of synchronization detect bit is set in the mi serial port channel status output register to indicate this condition. once this bit is set, then it will stay set until the descrambler achieves synchronization. a descrambler is not used for fx operation. 2.7.2 10 mbps a descrambler is not used in 10 mbps mode. 2.7.3 descrambler bypass the descrambler can be bypassed by setting the bypass scrambler/descrambler bit in the mi serial port channel con?uration register. when this bit is set, the data bypasses the descrambler and goes directly from the tp receiver to the 4b5b decoder. 2.8 twisted pair transmitter 2.8.1 100 mbps the tp transmitter consists of an mlt3 encoder, waveform generator and line driver. the mlt3 encoder converts the nrzi data from the scrambler into a three level code required by ieee 802.3. mlt3 coding uses three levels and converts 1's to transitions between the three levels, and converts 0's to no transitions or changes in level. the purpose of the waveform generator is to shape the transmit output pulse. the waveform generator takes the mlt3 three level encoded waveform and uses an array of switched current sources to control the shape of the twisted pair output signal in order to meet ieee 802.3 requirements. the output of the switched current sources then goes through a low pass ?ter in order to "smooth" the output and remove any high frequency components. in this way, the waveform generator preshapes the output waveform transmitted onto the twisted pair cable to meet the pulse template requirements outlined in ieee 802.3. the waveform generator eliminates the need for any external ?ters on the tp transmit output. the line driver converts the shaped and smoothed waveform to a current output that can drive 100 meters of category 5 unshielded twisted pair cable or 150 ohm shielded twisted pair cable. 2.8.2 10 mbps the tp transmitter operation in 10 mbps mode is much different than the 100 mbps transmitter. even so, the transmitter still consists of a waveform generator and line driver. the purpose of the waveform generator is to shape the output transmit pulse. the waveform generator consists of a rom, dac, clock generator, and ?ter. the dac generates a stair-stepped representation of the desired output waveform. the stairstepped dac output then goes through a low pass ?ter in order to "smooth" the dac output and remove any high frequency components. the dac values are determined from the rom output; the rom outputs are chosen to shape the pulse to the desired template and are clocked into the dac at high speed by the clock generator. in this way, the waveform generator preshapes the output waveform to be transmitted onto the twisted pair cable to meet the pulse template requirements outlined in ieee 802.3 clause 14 and also shown in figure 4. the waveshaper replaces and eliminates external ?ters on the tp transmit output. the line driver converts the shaped and smoothed waveform to a current output that can drive 100 meters of category 3/4/5 100 ohm unshielded twisted pair cable or 150 ohm shielded twisted pair cable, without any external ?ters. during the idle period, no output signal is transmitted on the tp outputs (except link pulse). 2.9 twisted pair receiver 2.9.1 receiver - 100 mbps the tp receiver detects input signals from the twisted pair input and converts it to a digital data bit stream ready for clock and data recovery. the receiver can reliably detect data from a 100base-tx compliant transmitter that has been passed through 0-100 meters of 100 ohm category 5 utp. the 100 mbps receiver consists of an adaptive equalizer, baseline wander correction circuit, comparators, and mlt- 3 decoder. the tp inputs ?st go to an adaptive equalizer. the adaptive equalizer compensates for the low pass characteristic of the cable, and it has the ability to adapt and compensate for 0-100 meters of category 5, 100 ohm utp. the baseline wander correction circuit restores the dc component of the input waveform that was removed by external transformers. the comparators convert the equalized signal back to digital levels and are used to qualify the data with the squelch circuit. the mlt-3 decoder takes the three level mlt-3 digital data from the comparators and converts it back to normal digital data to be used for clock and data recovery. 20 md400183/a 84225 0 102030405060708090100110 ?.0 ?.8 ?.6 ?.4 ?.2 0.0 0.2 0.4 0.6 0.8 1.0 time (ns) voltage (v) b c d a i j w v t g s q n o p e f m h r u l k reference time (ns) internal mau voltage (v) a00 b 15 1.0 c 15 0.4 d 25 0.55 e 32 0.45 f390 g 57 -1.0 h 48 0.7 i 67 0.6 j890 k 74 -0.55 l 73 -0.55 m61 0 n 85 1.0 o 100 0.4 p 110 0.75 q 111 0.15 r 111 0 s 111 -0.15 t 110 -1.0 u 100 -0.3 v 110 -0.7 w 90 -0.7 figure 4. tp output voltage template md400183/a 21 84225 2.9.2 receiver - 10 mbps the 10 mbps mode receiver is much simpler than the 100 mbps mode receiver and is identical to the 100 mbps receiver except: the adaptive equalizer is disabled and bypassed. the baseline wander correction circuit is disabled. the 10 mbps receiver is able to detect input signals from the twisted pair cable that are within the template speci?d in ieee 802.3 clause 14 and shown in figure 5. the output of the squelch comparator is used for squelch, link pulse detect, soi detect, reverse polarity detect. the data comparator is a zero crossing comparator whose output is used for clock and data recovery. 2.9.3 squelch - 100 mbps the squelch block determines whether the input contains valid data. the 100 mbps tx squelch is one of the criteria used to determine link intergrity. the squelch comparators compare the tx inputs against ?ed positive and negative thresholds, called squelch levels. the output from the squelch comparator goes to a digital squelch circuit, which determines whether the receive input data on that channel is valid. if the data is invalid, the receiver is in the squelched state. if the input voltage exceeds the squelch levels at least four times with alternating polarity within a 10 us interval, the data is considered to be valid by the squelch circuit and the receiver now enters into the unsquelch state. a. short bit b. long bit 3.1 v slope 0.5 v/ns 585 mv pw 0 3.1 v slope 0.5 v/ns 585 mv pw/4 0 3pw/4 pw 585 mv sin ( t/pw) * 585 mv sin ( t/pw) * 585 mv sin [2 (t - pw2)/pw] figure 5. tp input voltage template - 10 mbps 22 md400183/a 84225 in the unsquelch state, the receive threshold level is reduced by approximately 30% for noise immunity reasons and is called the unsquelch level. when the receiver is in the unsquelch state the input signal is considered valid. the device stays in the unsquelch state until loss of data is detected. loss of data is detected if no alternating polarity unsquelch transitions are detected during any 10 us interval. when the loss of data is detected, the receive squelch level is re-established. 2.9.4 squelch - 10 mbps the tp squelch algorithm for 10 mbps mode is identical to the 100 mbps mode, except: the 10 mbps squelch algorithm is not used for link integrity, but to sense the beginning of a packet. the receiver goes into the unsquelch state if the input voltage exceeds the squelch levels for three bit times with alternating polarity within a 50-250 ns interval. the receiver goes into the squelch state when soi is detected. unsquelch detection has no affect on link integrity, link pulses are used for that in 10 mbps mode. start of packet is determined when the receiver goes into the unsquelch state and crs is asserted. the receiver meets the squelch requirements de?ed in ieee 802.3 clause 14. 2.9.5 receive level adjust the receiver squelch and unsquelch levels can be lowered by 4.5 db by setting the receive level adjust bit in the mi serial port channel con?uration register. by setting this bit, the device can support cable lengths exceeding 100 meters. 2.10 fiber interface 2.10.1 general the fiber interface implements the 100basefx function de?ed in ieee 802.3. the fiber interface consists of three signals: (1) a differential pecl data output (fxop/fxon), (2) a differential pecl data input (fxip/fxin), and (3) a pecl signal detect (sd/fxen). the fiber interface section consists of four blocks: (1) transmitter, (2) receiver, (3) signal detect, and (4) far end fault. the fiber interface can be independently selected for each channel with the sd/fxen_[3:0] pins. the fiber interface is disabled in 10mbps mode. autonegotiation and the scrambler/descrambler are disabled when the fiber interface is enabled. the fiber interface meets all ieee 802.3 requirements. 2.10.2 transmitter the fx transmitter converts data from the 4b5b encoder into binary nrzi data and outputs the data onto the fxop/fxon pins for each channel. the output driver is a differential current source that will drive a 100 ohm load to ecl levels. the fxop/fxon pins can directly drive an external ?er optic transceiver. the fx transmitter meets all the requirements de?ed in ieee 802.3. the fx transmit output current level is derived from an internal reference voltage and the external resistor on rext pin. 2.10.3 receiver the fx receiver (1) converts the differential ecl inputs on the fxip/fxin pins for each channel to a digital bit stream, (2) validates the data on fxip/fxin with the sd/ fxen input pin for each channel, and (3) enable/disables the fiber interface with the sd/fxen pin for each channel. the fx receiver meets all requirements de?ed in ieee 802.3. the input to the fxip/fxin pins can be directly driven from a ?er optic transceiver and ?st goes to a comparator. the comparator compares the input waveform against the internal ecl threshold levels to produce a low jitter serial bit stream with internal logic levels. the data from the comparator output is then passed to the clock and data recovery block provided the signal detect input, sd/fxen, is asserted. the signal detect function is described in the next section. 2.10.4 signal detect the fx receiver has a signal detect input pin, sd/fxen, for each channel which indicates whether the incoming data on fxip/fxin is valid or not for that channel. the sd/fxen pin can be driven directly from an external ?er optic transceiver and meets all requirements de?ed in the ieee 802.3 speci?ations. md400183/a 23 84225 the sd/fxen input goes directly to a comparator. the comparator compares the input waveform against the internal ecl threshold level to produce a digital signal with internal logic levels. the output of the signal detect comparator then goes to the link integrity and squelch blocks. if the signal detect input is asserted, the channel is placed in the link pass state and the input data on fxip/fxin is determined to be valid. if the signal detect input is deasserted, the channel is placed in the link fail state and the input data on fxip/fxin is determined to be invalid. the sd_thr pin adjusts the ecl trip point of the sd/ fxen input. when the sd_thr pin is tied to a voltage between gnd and gnd+0.45v, the trip point of the sd ecl input buffer is internally set to vcc-1.3v. when sd_thr pin is set to a voltage greater than gnd+0.85v, the trip point of the sd sd/fxen ecl input buffer is set to the voltage that is applied to the sd_thr pin. the trip level for the sd/fxen input buffer must be set to vcc- 1.3v. having external control of the sd/fxen buffer trip level with the sd_thr pin allows this trip level to be referenced to an external supply which facilitates connection to both 3.3v and 5v external ?er optic transceiver. if the device is to be connected to a 3.3v external ?er optic transceiver, then sd_thr should be tied to gnd. if the device is to be connected to a 5v external ?er optic transceiver, then sd_thr needs to be tied to vcc-1.3v, and this can be done so with an external resistor divider. refer to the applications section for more details on connections to external ?er optic transceivers. 2.10.5 fiber interface disable the fiber interface will be disabled if the sd/fxen pin is tied to gnd. disabling the fiber interface automatically enables the tp interface. 2.10.6 far end fault each channel has the far end fault capability, referred to as fef, de?ed in ieee 802.3 speci?ations. fef is a method by which the fiber interface can signal a fault to a remote device by transmitting an idle pattern consisting of 84 ? s followed by a single ? repeatedly (idle period normally has all 1 s). fef was speci?d in ieee 802.3 because fx lacks the autonegotiation capability to signal a remote fault to another station. fef can only be made operational only when the fiber interface is enabled. in the device default state with the fiber interface enabled, fef is disabled, but it can be enabled by setting the fef select bit in the mi serial port global con?uration register. when fef is enabled, (1) a ? is transmitted after each group of 84 ? s repeatedly during idle if the sd/fxen pin is deasserted, and (2) if an fef stream is detected by the receiver for 3 consecutive intervals, the remote fault bit is set in the mi serial port status register and the led0 output pin is asserted. 2.11 collision 2.11.1 100 mbps collision occurs whenever transmit and receive occur simultaneously while the device is in half duplex. collision is sensed whenever there is simulaneous transmission (packet transmission on tpop/n) and reception (non idle symbols detected on receive input). when collision is detected: the col output is asserted. tp data continues to be transmitted on twisted pair outputs. tp data continues to be received on twisted pair inputs. internal crs loopback is disabled. once collision starts, crs is asserted and stays asserted until the receive and transmit packets that caused the collision are terminated. the collision function is disabled if the device is in the full duplex mode, is in the link fail state, or if the device is in the diagnostic loopback mode. 2.11.2 10 mbps collision in 10 mbps mode is identical to the 100 mbps mode, except: reception is detemined by the 10 mbps squelch criteria. rxd[3:0] outputs are forced to all 0's. collision is asserted when the sqe test is performed. collision is asserted when the jabber condition has been detected. 2.11.3 collision test the controller interface collision signal, col, can be tested by setting the collision test register bit in the mi serial port control register. when this bit is set, txen is looped back onto col and the tp outputs are disabled. 2.11.4 collision indication collision can be programmed to appear on the led2 pin by appropriately setting the led de?ition bits in the mi serial port global con?uration register. the led drivers section describes the programmable led de?ition bit settings. when the led2 pin is programmed to be a collision detect output, the pin is asserted low for 100 ms every time a collision occurs. 24 md400183/a 84225 2.12 start of packet 2.12.1 100 mbps start of packet for 100 mbps mode is indicated by a unique start of stream delimiter (ssd). the ssd pattern consists of the two /j/k/ 5b symbols inserted at the beginning of the packet in place of the ?st two preamble symbols, as de?ed in ieee 802.3 clause 24 and shown in table 2 and figure 2. the transmit ssd is generated by the 4b5b encoder and the /j/k/ symbols are inserted by the 4b5b encoder at the beginning of the transmit data packet in place of the ?st two 5b symbols of the preamble, as shown in figure 2. the receive pattern is detected by the 4b5b decoder by examining groups of 10 consecutive code bits (two 5b words) from the descrambler. between packets, the receiver will be detecting the idle pattern, which is 5b /i/ symbols. while in the idle state, crs and rxdv are deasserted. if the receiver is in the idle state and 10 consecutive code bits from the receiver consist of the /j/k/ symbols, the start of packet is detected, data reception is begun, crs and rxdv are asserted, and /5/5/ symbols are substituted in place of the /j/k/ symbols. if the receiver is in the idle state and 10 consecutive code bits from the receiver consist of a pattern that is neither /i/ i/ nor /j/k/ symbols but contains at least 2 non-contiguous 0's, then activity is detected but the start of packet is considered to be faulty and a false carrier indication (also referred to as bad ssd) is signalled to the controller interface. when false carrier is detected crs is asserted, rxdv remains deasserted, rxd[3:0]=1110 while rxer is asserted, and the bad ssd bit is set in the mi serial port channel status output register. once a false carrier event is detected, the idle pattern (two /i/i/ symbols) must be detected before any new ssd s can be sensed. if the receiver is in the idle state and 10 consecutive code bits from the receiver consist of a pattern that is neither /i/ i/ nor /j/k/ symbols but does not contain at least 2 non contiguous 0's, the data is ignored and the receiver stays in the idle state. 2.12.2 10 mbps since the idle period in 10 mbps mode is de?ed to be no data on the tp inputs, then the start of packet for 10 mbps mode is detected when valid data is detected by the tp squelch circuit. when start of packet is detected, crs is asserted as described in the controller interface section. refer to the tp squelch - 10 mbps section for the algorithm for valid data detection. 2.13 end of packet 2.13.1 100 mbps end of packet for 100 mbps mode is indicated by an end of stream delimiter (referred to as esd). the esd pattern consists of the two /t/r/ 4b5b symbols inserted after the end of the packet, as de?ed in ieee 802.3 clause 24 and shown in table 2 and figure 2. the transmit esd is generated by the 4b5b encoder and the /t/r/ symbols are inserted by the 4b5b encoder after the end of the transmit data packet, as shown in figure 2. the receive esd pattern is detected by the 4b5b decoder by examining groups of 10 consecutive code bits (two 5b words) from the descrambler during valid packet reception to determine whether there is an esd. if the 10 consecutive code bits from the receiver during valid packet reception consist of the /t/r/ symbols, the end of packet is detected, data reception is terminated, crs and rxdv are deasserted, and /i/i/ symbols are substituted in place of the /t/r/ symbols. if 10 consecutive code bits from the receiver during valid packet reception do not consist of /t/r/ symbols, but consist of /i/i/ symbols instead, the packet is considered to have been terminated prematurely and abnormally. when this premature end of packet condition is detected, rxer remains asserted for the nibble associated with the ?st /i/ symbol detected and then rxer and crs and rxdv are all deasserted. premature end of packet condition is also indicated by setting the esd error bit in the mi serial port channel status output register. 2.13.2 10 mbps the end of packet for 10 mbps mode is indicated with the soi (start of idle) pulse. the soi pulse is a positive double wide pulse containing a manchester code violation inserted at the end of every packet. the transmit soi pulse is generated by the tp transmitter and inserted at the end of the data packet after txen is deasserted. the transmitted soi output pulse at the tp output is shaped by the transmit waveshaper to meet the pulse template requirements speci?d in ieee 802.3 clause 14 and shown in figure 6. the receive soi pulse is detected by the tp receiver by sensing missing data transitions. once the soi pulse is detected, data reception is ended and crs and rxdv are deasserted. md400183/a 25 84225 0 bt 4.5 bt 6.0 bt +50 mv 45.0 bt 4.5 bt 2.5 bt 2.25 bt 0.25 bt 0.5 v/ns 3.1 v ?0 mv 585 mv ?.1 v 585 mv sin(2 (t/1bt)) 0 t 0.25 bt and 2.25 t 2.5 bt * ** 0 bt 1.3 bt 2.0 bt 4.0 bt +50 mv ?0 mv 4.0 bt 42.0 bt 3.1 v 0.5 v/ns 0.5 bt 0.6 bt 300 mv 200 mv 585 mv +50 mv ?0 mv 2.0 bt 0.85 bt ?.1 v 0.25 bt figure 6. soi output voltage template - 10 mbps figure 7. link pulse output voltage template - 10 mbps 26 md400183/a 84225 2.14 link integrity & autonegotiation 2.14.1 general the 84225 can be con?ured to implement either the standard link integrity algorithms or the autonegotiation algorithm. the standard link integrity algorithms are used solely to establish an active link to and from a remote device. there are different standard link integrity algorithms for 10 and 100 mbps modes. the autonegotiation algorithm is used for two purposes: ?to automatically con?ure the device for either 10/100 mbps and half/full duplex modes ?establish an active link to and from a remote device the standard link integrity and autonegotiation algorithms are described below. 2.14.2 10base-t link integrity algorithm the 84225 uses the same 10base-t link integrity algorithm that is de?ed in ieee 802.3 clause 14. this algorithm uses normal link pulses, referred to as nlp s and transmitted during idle periods, to determine if a device has successfully established a link with a remote device (called link pass state). the transmit link pulse meets the template de?ed in ieee 802.3 clause 14 and shown in figure 7. refer to ieee 802.3 clause 14 for more details if needed. 2.14.3 100base-tx link integrity algorithm since 100base-tx is de?ed to have an active idle signal, then there is no need to have separate link pulses like those de?ed for 10base-t. the 84225 uses the squelch criteria and descrambler synchronization algorithm on the input data to determine if the device has successfully established a link with a remote device (called link pass state). refer to ieee 802.3 for details on both algorithms. 2.14.4 autonegotiation algorithm as stated previously, the autonegotiation algorithm is used for two purposes: ?to automatically con?ure the device for either 10/100 mbps and half/full duplex modes ?to establish an active link to and from a remote device the autonegotiation algorithm is the same algorithm that is de?ed in ieee 802.3 clause 28. autonegotiation uses a burst of link pulses, called fast link pulses and referred to as flp s, to pass up to 16 bits of signaling back and forth between the 84225 and a remote device. the transmit tx_di tx_di a.) normal link pulse (nlp) b.) fast link pulse (flp) d0 d15 d14 d3 d2 d1 clock clock clock clock clock clock clock data data data data data data figure 8. nlp vs. flp link pulse md400183/a 27 84225 flp pulses meet the template speci?d in ieee 802.3 and shown in figure 7. a timing diagram contrasting nlp s and flp s is shown in figure 8. the autonegotiation algorithm is initiated by any of the following events: ?powerup ?device reset ?autonegotiation reset ?entering the link fail state once a negotiation has been initiated, the 84225 ?st determines if the remote device has autonegotiation capability. if the device is not autonegotiation capable and is just transmitting either a 10base-t or 100base-tx signal, the 84225 will sense that and place itself in the correct mode. if the 84225 detects flp s from the remote device, then the remote device is determined to have autonegotiation capability and the device then uses the contents of the mi serial port autonegotiation advertisement register and flp s to advertise it s capabilies to a remote device. the remote device does the same, and the capabilities read back from the remote device are stored in the mi serial port autonegotiation remote end capability register. the 84225 negotiation algorithm then matches it s capabilities to the remote devices capabilities and determines to what mode the device should be con?ured according to the priority resolution algorithm de?ed in ieee 802.3 clause 28. once the negotiation process is completed, the 84225 then con?ures itself for either 10 or 100 mbps mode and either full or half duplex modes (depending on the outcome of the negotiation process), and it switches to either the 100base-tx or 10base-t link integrity algorithms (depending on which mode was enabled by autonegotiation). refer to ieee 802.3 clause 28 for more details. 2.14.5 autonegotiation outcome indication the outcome or result of the autonegotiation process is stored in the speed detect and duplex detect bits in the mi serial port status output register. 2.14.6 autonegotiation status the status of the autonegotiation process can be monitored by reading the autonegotiation acknow- ledgement bit in the mi serial port status register. 2.14.7 autonegotiation enable the autonegotiation algorithm can be enabled (or restarted) by setting the autonegotiation enable bit in the mi serial port control register or by asserting the aneg pin. the autonegotiatiopn enable bit and aneg pin both have to be high to enable autonegotiation. when the autonegotiation algorithm is enabled, the device halts all transmissions including link pulses for 1200-1500 ms, enters the link fail state, and restarts the negotiation process. when the autonegotiation algorithm is disabled, the selection of 100 mbps or 10 mbps mode is determined by the speed select bit in the mi serial port control register, and the selection of half or full duplex is determined by the duplex select bit in the mi serial port control register. 2.14.8 autonegotiation reset the autonegotiation algorithm can be initiated at any time by setting the autonegotiation reset bit in the mi serial port control register. 2.14.9 link indication receive link detect activity can be monitored through the link detect bit in the mi serial port status and status output registers or it can also be programmed to appear on led status pins by appropriately setting the programmable led select bits in the mi serial port con?uration 2 register as shown in table 3. whenever the led status pins are programmed to be a link detect output, these pins are asserted low whenever the device is in the link pass state. 2.14.10 link disable the link integrity function can be disabled by setting the link disable bit in the mi serial port con?uration 1 register. when the link integrity function is disabled, the device is forced into the link pass state, con?ures itself for half/full duplex based on the value of the duplex bit in the mi serial port control register, con?ures itself for 100/ 10 mbps operation based on the values of the speed bit in the mi serial port control register, and continues to transmit nlp s or tx idle patterns, depending on whether the device is in 10 or 100 mbps mode. 2.15 jabber 2.15.1 100 mbps the jabber function is disabled in the 100 mbps mode. 2.15.2 10 mbps a jabber condition occurs when the transmit packet exceeds a predetermined length. when jabber is detected, the tp transmit outputs are forced to the idle state, collision is asserted, and jabber register bits in the mi serial port status and channel status output registers are set. 28 md400183/a 84225 2.16 receive polarity correction 2.16.1 100 mbps no polarity detection or correction is needed in 100 mbps mode. 2.16.2 10 mbps the polarity of the signal on the tp receive input is continuously monitored. if one soi pulse indicates incorrect polarity on the tp receive input, the polarity is internally determined to be incorrect, and the reverse polarity bit is set in the mi serial port channel status output register. the 84225 will automatically correct for the reverse polarity condition provided that the autopolarity feature is not disabled. 2.17 full duplex mode 2.17.1 100 mbps full duplex mode allows transmission and reception to occur simultaneously. when full duplex mode is enabled, collision is disabled, and internal txen to crs loopback is disabled. the device can be either forced into half or full duplex mode, or the device can detect either half or full duplex capability from a remote device and automatically place itself in the correct mode. each channel can be forced into the full or half duplex modes by either setting the duplex bit in the mi serial port control register or asserting the dplx pin for the corresponding channel with autonegotiation disabled. the device can automatically con?ure itself for full or half duplex modes by using the autonegotiation algorithm to advertise and detect full and half duplex capabilities to and from a remote terminal. for detailed information, refer to the link integrity & autonegotiation section. 2.17.2 10 mbps full duplex in 10 mbps mode is identical to the 100 mbps mode. 2.17.3 full duplex indication full duplex detect activity can be monitored through the duplex detect bit in the mi serial port channel status output register. full duplex detect activity also appears on the led1 pin by default. the led outputs can be programmed to indicate four speci? sets of events, by appropriately setting the led de?ition bits in the mi serial port global con?uration register. the led drivers section describes the programmable led de?ition bit settings. note that full duplex detection appears on the led1 pin in each of the four sets of events. the led1 pin is asserted low when the device is con?ured for full duplex operation. 2.18 10/100 mbps selection 2.18.1 general the device can be forced into either the 100 or 10 mbps mode, or the device can detect 100 or 10 mbps capability from a remote device and automatically place itself in the correct mode. the device can be forced into either the 100 or 10 mbps mode by either setting the speed select bit in the mi serial port control register or by setting the speed pin with autonegotiation disabled. both the speed select bit and speed pin need to be set to the same speed (10 or 100) for the device to be properly con?ured. the speed select bit and speed pin are ignored if autonegotiation is enabled. the device can automatically con?ure itself for 100 or 10 mbps mode by using the autonegotiation algorithm to advertise and detect 100 and 10 mbps capabilities to and from a remote device. refer to the link integrity & autonegotiation section for more details on autonegotiation. 2.18.2 10/100 mbps indication the device speed (100/10 mbps) can be monitored through the speed bit in the mi serial port channel status output register. the device speed can also be programmed to appear on the led0 pin, by appropriately setting the led de?ition bits in the mi serial port global con?uration register. the led drivers section describes the programmable led de?ition bit settings. when the led0 pin is programmed to be a speed detect output, the pin is asserted low when the device is con?ured for 100 mbps operation. 2.19 loopback 2.19.1 internal crs loopback txen is internally looped back onto crs during every transmit packet. this internal crs loopback is disabled during collision, in full duplex mode, in link fail state, and in rmii mode. in 10 mbps mode, internal crs loopback is also disabled when jabber is detected. md400183/a 29 84225 the internal crs loopback can be disabled by setting the txen to crs loopback disable bit in the mi serial port channel con?uration register. when this bit is set, txen is no longer looped back to crs. 2.19.2 diagnostic loopback a diagnostic loopback mode can also be selected by setting the loopback bit in the mi serial port control register. when diagnostic loopback is enabled, txd[3:0] data is looped back onto rxd[3:0], txen is looped back onto crs, rxdv operates normally, the tp receive and transmit paths are disabled, the transmit link pulses are halted, and the half/full duplex modes do not change. diagnostic loopback mode can not be enabled when the fbi interface is selected. 2.20 reset the 84225 is reset when either: (1) vdd is applied to the device, (2) the reset bit is set in the mi serial port control register, or (3) the reset pin is asserted active low. when the reset is initiated by either (1) or (2), an internal power-on reset pulse is generated which resets all internal circuits, forces the mi serial port bits to their default values, and latches in new values for the mi address. after the power-on reset pulse has ?ished, the reset bit in the mi serial port control register is cleared and the device is ready for normal operation. the device is guaranteed to be ready for normal operation 50 ms after the reset was initiated. when the reset is initiated by (3), the identical procedure takes place as in (1) and (2), except the device stays in reset until the reset pin is deasserted high. 2.21 powerdown the 84225 can be powered down by setting the powerdown bit in the mi serial port control register. in powerdown mode, the tp outputs are in high impedance state, all functions are disabled except the mi serial port, and the power consumption is reduced to a minimum. the device will be ready for normal operation 50 ms after powerdown is deasserted. 2.22 clock the 84225 requires a 25 mhz reference frequency for internal signal generation in mii mode, and 50 mhz in rmii mode. this reference frequency must be applied to the clkin pin. 2.23 led drivers the led[3:0] outputs can drive led s tied to either vdd or gnd. the led de?itions assume that the led outputs are active low. if the led anodes are tied to the positive power supply (through limiting resistors), the led will indicate the event as shown in table 3. if the led cathodes are tied to ground and the anodes to the 84225 driver output, they will indicate the respective complementary events. the led[3:0] outputs can also drive other digital inputs. table 3. led function de?ition notes: when the fx interface is enabled, led0 becomes fef. default = 000 when pin leddef = 0 bits 16. [13:11] forced to 001 when pin leddef = 1 table 4. led event de?ition leddef led3 led2 led1 led0 1 link + act col fdx 10/100 0 link 100 act fdx link10 symbol de?ition act activity occurred, stretch pulse to 100 ms col collision occurred, stretch pulse to 100 ms link100 100 mb link detected link10 10 mb link detected link 100 mb or 10 mb link detected link+act led on if link detected (10 or 100). led blinks if activity determined, stretch pulse to 100 ms fdx full duplex mode detected with link pass 10/100 10 mb mode enabled (high) or 100 mb mode enabled (low) with link pass 30 md400183/a 84225 2.24 repeater mode the 84225 has one prede?ed repeater mode which can be enabled by asserting the repeater pin. when this mode is enabled the device operation is altered as follows: txen to crs loopback is disabled. 2.25 mi serial port 2.25.1 signal description the mi serial port has ?e pins, mdc, mdio, and phyad[4:2]. mdc is the serial shift clock input. mdio is a bidirectional data i/o pin. phyad[4:2] are physical address pins. pins phyad[4:2] set the three most signi?ant bits of the phy address. the two least signi?ant bits of the phy address are set internally to match the channel number, as shown in table 5. table 5. phyad[1:0] settings 2.25.2 timing figure 10 shows a timing diagram for a mi serial port cycle. the mi serial port is idle when at least 32 continuous 1's are detected on mdio and remains idle as long as continuous 1's are detected. during idle, mdio is in the high impedance state. when the mi serial port is in the idle state, a 01 pattern on the mdio pin initiates a serial shift cycle. data on mdio is then shifted in on the next 14 rising edges of mdc (mdio is high impedance). if the register access mode is not enabled, on the next 16 rising edges of mdc, data is either shifted in or out on mdio, depending on whether a write or read cycle was selected with the bits read and write. after the 32 mdc cycles have been completed, one complete register has been phyad1 phyad0 channel 3 11 channel 2 10 channel 1 01 channel 0 00 read/written, the serial shift process is halted, data is latched into the device, and mdio goes into high impedance state. another serial shift cycle cannot be initiated until the idle condition (at least 32 continuous 1's) is detected. 2.25.3 multiple register access multiple registers can be accessed on a single mi serial port access cycle with the multiple register access feature. the multiple register access feature can be enabled by setting the multiple register access enable bit in the global con?uration register for all channels. when multiple register access is enabled, all registers can be accessed on a single mi serial port access cycle by setting the register address to 11111 during the ?st 16 mdc clock cycles. there is no actual register residing in register address location 11111. when the register address is set to 11111, all eleven registers are accessed for all four channels on the 704 rising edges of mdc (4 x 11 x 16) that occur after the ?st 16 mdc clock cycles of the mi serial port access cycle. the registers are accessed in numerical order from 0 to 20 for each channel and from channel 0 to 3. after all 720 mdc clocks have been completed, all the registers have been read/written, and the serial shift process is halted, data is latched into the device, and mdio goes into high impedance state. another serial shift cycle cannot be initiated until the idle condition (at least 32 continuous 1's) is detected. 2.25.4 bit types since the serial port is bidirectional, there are many types of bits. the bit type de?itions are summarized in table 6. write bits (w) are inputs during a write cycle and are high impedance during a read cycle. read bits (r) are outputs during a read cycle and high impedance during a write cycle. read/write bits (r/w) are actually write bits that can be read out during a read cycle. r/wsc bits are r/w bits that are self clearing after a set period of time or after a speci? event has completed. r/ll bits are read bits that latch themselves when they go low, and they stay latched low until read. after they are read, they are reset high. r/lh bits are the same as r/ll bits, except that they latch high. r/lt are read bits that latch themselves md400183/a 31 84225 figure 10. mi serial port frame timing diagram mdio mdc 02 134 7 6 589 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 00 11 p4 p1 p2 p3 p0 r4 r3 r2 r1 r0 10 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 st op phyad regad ta data write cycle mdio mdc 02 134 7 6 589 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 00 11 p4 p1 p2 p3 p0 r4 r3 r2 r1 r0 z 0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 st op phyad regad ta data read cycle write bits phy clocks in data on rising edges of mdc with t = 10ns min t = 10ns min s h write bits phy clocks in data on rising edges of mdc with t = 10ns min t = 10ns min s h read bits phy clocks out data on rising edges of mdc with t = 20ns max d 32 md400183/a 84225 whenever they make a transition or change value, and they stay latched until they are read. after r/lt bits are read, they are updated to their current value. the r/lt bits can also be programmed to assert the interrupt function as described in the interrupt section. table 6. mi register bit type de?ition symbol name de?ition write cycle read cycle w write input no operation, hi z r read no operation, hi z output r/w read/write input output r/ wsc read/ write self clear- ing input clears itself after opera- tion com- pleted output r/ll read/ latching low no operation, hi z output when bit goes low, bit latched. when bit is read, bit updated. r/lh read/ latching high no operation, hi z output when bit goes high, bit latched. when bit is read, bit updated. r/lt read/ latching on transi- tion no operation, hi z output when bit transitions, bit latched and interrupt set when bit is read, interrupt cleared and bit updated. 2.25.5 frame structure the structure of the serial port frame is shown in table 7 and a timing diagram is shown in figure 10. each serial port access cycle consists of 32 bits (or 720 bits if multiple register access is enabled and regad[4:0]=11111), exclusive of idle. the ?st 16 bits of the serial port cycle are always write bits and are used for addressing. the last 16/704 bits are from one/all of the 4 x 11 data registers. the ?st 2 bits in table 7 and figure 10 are start bits and need to be written as a 01 for the serial port cycle to continue. the next 2 bits are read and write bits which determine whether the accessed data register bits will be read or write. the next 5 bits are device addresses. the 3 most signi?ant bits must match the values on pins phyad[4:2] and the 2 least signi?ant bits select one of four channels for access. the next 5 bits are register address select bits which select one of the eleven registers for access. the next 2 bits are turnaround bits which are not an actual register bits but extra time to switch mdio from write to read if necessary. the ?al 16 bits of the mi serial port cycle (or 704 bits if multiple register access is enabled and regad[4:0]=11111) come from the speci? data register designated by the register address bits regad[4:0]. 2.25.6 register structure the 84225 has eleven 16 bit registers for each channel. all eleven registers are available for setting con?uration inputs and reading status outputs. a map of the registers is shown in table 8. the eleven registers consist of six registers that are de?ed by ieee 802.3 speci?ations (registers 0-5) and ?e registers that are unique to the 84225 (registers 16-20). the structure and bit de?ition of the control register is shown in table 9. this register stores various con?uration inputs and its bit de?ition complies with the ieee 802.3 speci?ations. md400183/a 33 84225 the structure and bit de?ition of the status register is shown in table 10. this register contains device capabilities and status output information and its bit de?ition complies with the ieee 802.3 speci?ations. the structure and bit de?ition of the phy id register 1 and phy id register 2 is shown in table 11 and table 12, respectively. these registers contain an identi?ation code unique to the 84225 and their bit de?ition complies with the ieee 802.3 speci?ations. the structure and bit de?ition of the auto negotiation advertisement and auto negotiation remote end capability registers is shown in table 13 and table 14, respectively. these registers are used by the auto negotiation algorithm and their bit de?ition complies with the ieee 802.3 speci?ations. the structure and bit de?ition of the global con?uration register is shown in table 15. this register is common for all four channels. it stores various con?uration inputs. the structure and bit de?ition of the channel con?uration register is shown in table 16. this register stores various con?uration inputs unique to each channel. the structure and bit de?ition of the channel status output register is shown in table 17. this register contains output status information from each channel. the structure and bit de?ition of the global interrupt mask register is shown in table 18. this register is common for all four channels. bit 7 is the interrupt indication. the 7 least signi?ant bits are the mask bits for the r/lt status bits in the channel status output register. register 20 in table 19 is reserved for factory use only. all bits must be set to the pre-set default states shown for normal operation. 2.25.7 invalid registers the registers in locations 6-15 and 21-31 are not implemented on the device, hence unused. when an unused register is read, the value returned can be con?ured to be either all 0s or all 1s by appropriately pinstrapping the regdef pin. 34 md400183/a 84225 internal interrupt mdc mdio mdio hi-z pulled high externally mdio hi-z pulled high externally interrupt pulse internal interrupt mdc mdio last two bits of read cycle mdio hi-z pulled high externally interrupt pulse mdio hi-z pulled high externally b0 b1 figure 11. mdio interrupt pulse md400183/a 35 84225 3.0 register description table 7. mi serial port structure mi registers - address and default value 36 md400183/a 84225 r/lt r r/lt r/lt r/lt r/lt r/lt r/lt 1 0 r r rr r rr r 11/10/01/00 11/10/01/00 0 0 00 0 0 00 00 0 0 x.6 x.7 x.8 x.9 x.13 x.10 x.15 x.14 x.11 x.12 x.3 x.0 x.5 x.4 x.1 x.2 r r/wsc rr r r r r 0 0 r/w r/wsc r/w r/w r/wsc r/w r/w r/w 0 0 10 00 0 1 00 00 0 0 control status autonegot. advertisement phy id #2 phy id #1 autonegot. remote capability channel status output reserved reserved table 8. mi serial port register map 0 coltst dplx aneg_rst speed rst lpbk pdn aneg_en 00 00 0 0 mii_dis cap_supr 0 0 0 cap_txh cap_t4 cap_txf cap_th cap_tf cap_aneg jab aneg_ack rem_flt exreg link 0 r r rr r r/lh r/lh r/ll 0 0 r r rr r rr r 0 0 10 01 1 1 11 00 0 0 oui12 oui11 oui10 oui9 oui5 oui3 oui4 oui7 oui6 oui15 oui17 oui13 oui14 oui18 oui16 oui8 r r rr r r r r 0 0 r r rr r rr r 0 0 00 00 0 0 00 01 1 1 part2 part3 part4 part5 oui21 oui19 oui20 oui23 oui22 rev3 rev1 part1 part0 rev0 rev2 oui24 r r rr r r r r 1 0 r r rr r rr r 0 0 10 11 1 1 00 10_fdx tx_hdx tx_fdx t4 rf np ack 0 0 00 00 csma 0 pause r/w r/w r/w r/w r/w r/w r/w r/w 1 1 r/w r/w r/w r/w r/w r r/w r/w 1 0 00 00 0 0 01 10 0 0 10_fdx tx_hdx tx_fdx t4 rf np ack 0 0 00 00 csma 0 pause r r rr r r r r 0 0 r r rr r rr r 0 0 00 00 0 0 00 00 0 1 0 0 0 0 0 00 0 1 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 00 00 0 0 10 00 0 0 0 00 0 0 r/w r/w r/w r/w r/w 0 r/w 0 0 0 r/w 0 00 0 0 link_fail 0 chad0 chad1 0 rpol dsyn_to 0 0 cwrd esd spd_det dplx_det jab ssd 0 0 1 4 3 2 5 16 18 17 0 r/w 0 0 r/w 0 0 r/w 0 1 r/w 1 000 0 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 0 reserved r/w r/w r/w r/w r/w r/w r/w r/w 1 0 r/w r/w r/w r/w r/w r/w r/w 0 0 00 00 0 11 11 1 1 19 r/w 0 0 reserved 0 0 0 0 0 00 0 00 0 r/w r/w r/w r/w 0 0 r/w r/w r/w r/w r/w r/w 0 0 00 r/w 00 0 0 r/w 0 00 20 0 r/w 0 0 0 0 r/w 0 r/w 0 r/w 0 111 1 1 1 1 00 00 0 0 0 00 md400183/a 37 84225 note: 0.15 bit is shifted first 0.15 0.14 0.13 0.12 0.11 0.10 0.9 0.8 rst lpbk speed aneg_en pdn mii_dis aneg_rst dplx r/wsc r/w r/w r/w r/w r/w r/wsc r/w 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 coltst0000000 r/wsc rrrrrrr bit symbol name de?ition r/w default 0.15 rst reset 1 = reset, bit self clearing after reset completed 0 = normal r/wsc 0 0.14 lpbk loopback enable 1 = loopback mode enabled 0 = normal r/w 0 0.13 speed speed select 1 = 100 mbps selected (100basetx) 0 = 10 mbps selected (10baset) note: this bit can be overridden with speed pin. r/w 1 0.12 aneg_en auto negotiation enable 1 = auto negotiation enabled 0 = auto negotiation disabled note: this bit can be overridden with aneg pin. r/w 1 0.11 pdn power down enable 1 = power down 0 = normal r/w 0 0.10 mii_dis mii interface disable 1 = mii interface disable 0 = normal r/w 0 0.9 aneg_rst auto negotiation reset 1 = restart auto negotiation process, bit self clearing after reset completed 0 = normal r/wsc 0 0.8 dplx duplex mode select 1 = full duplex 0 = half duplex note: this bit can be overridden with dplx pin. r/w 0 0.7 coltst collision test enable 1 = collision test enabled 0 = normal r/w 0 0.6 through 0.0 reserved r 0 table 9. register 0 ?control register de?ition 38 md400183/a 84225 note: 1.15 bit is shifted first 1.15 1.14 1.13 1.12 1.11 1.10 1.9 1.8 cap_t4 cap_txf cap_txh cap_tf cap_th 0 0 0 rrrrrrrr 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0 cap_supr aneg_ack rem_flt cap_aneg link jab exreg r r r r/lh r r/ll r/lh r bit symbol name de?ition r/w default 1.15 cap_t4 100baset4 capable 0 = not capable of 100baset4 operation r 0 1.14 cap_txf 100basetx full duplex capable 1 = capable of 100basetx full duplex r 1 1.13 cap_txh 100basetx half duplex capable 1 = capable of 100basetx half duplex r 1 1.12 cap_tf 10baset full duplex capable 1 = capable of 10baset full duplex r 1 1.11 cap_th 10baset half duplex capable 1 = capable of 10baset half duplex r 1 1.10 through 1.7 reserved r 0 1.6 cap_supr mi preamble suppression capable 0 = not capable of accepting mi frames with preamble suppression r0 1.5 aneg_ack auto negotiation acknowledgment 1 = auto negotiation acknowledgment process complete 0 = auto negotiation not complete r0 1.4 rem_flt remote fault detect 1 = remote fault detect. this bit is set when remote fault bit 5.13 is set. 0 = no remote fault r/lh 0 1.3 cap_aneg auto negotiation capable 1 = capable of auto negotiation r 1 1.2 link link status 1 = link detect (same as bit 18.6 inverted) 0 = link not detect r/ll 0 1.1 jab jabber detect 1 = jabber detect 0 = normal r/lh 0 1.0 exreg extended register capable 1 = extended registers exist r 1 table 10. register 1- status register de?ition md400183/a 39 84225 note: 2.15 bit is shifted first 2.15 2.14 2.13 2.12 2.11 2.10 2.9 2.8 oui3 oui4 oui5 oui6 oui7 oui8 oui9 oui10 rrrrrrrr 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2.0 oui11 oui12 oui13 oui14 oui15 oui16 oui17 oui18 rrrrrrrr bit symbol name de?ition r/w default 2.15 2.14 2.13 2.12 2.11 2.10 2.9 2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2.0 oui3 oui4 oui5 oui6 oui7 oui8 oui9 oui10 oui11 oui12 oui13 oui14 oui15 oui16 oui17 oui18 company id, bits 3-18 seeq oui = 00-a0-7d r 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 tabel 11. register 2 - phy id register 1 de?ition 40 md400183/a 84225 note: 3.15 bit is shifted first 3.15 3.14 3.13 3.12 3.11 3.10 3.9 3.8 oui19 oui20 oui21 oui22 oui23 oui24 part5 part4 rrrrrrrr 3.7 3.6 3.5 3.4 3.3 3.2 3.1 3.0 part3 part2 part1 part0 rev3 rev2 rev1 rev0 rrrrrrrr bit symbol name de?ition r/w default 3.15 3.14 3.13 3.12 3.11 3.10 oui19 oui20 oui21 oui22 oui23 oui24 company id, bits 3-18 seeq oui = 00-a0-7d r 1 1 1 1 1 0 3.9 3.8 3.7 3.6 3.5 3.4 pa rt 5 pa rt 4 pa rt 3 pa rt 2 pa rt 1 pa rt 0 manufacturer s part number 04 r 0 0 0 1 0 0 3.3 3.2 3.1 3.0 rev3 rev2 rev1 rev0 manufacturer s revision number r table 12. register 3 - phy id register 2 de?ition md400183/a 41 84225 note: 4.15 bit is shifted first 4.15 4.14 4.13 4.12 4.11 4.10 4.9 4.8 np ack rf 0 0 pause t4 tx_fdx r/w r r/w r/w r/w r/w r/w r/w 4.7 4.6 4.5 4.4 4.3 4.2 4.1 4.0 tx_hdx 10_fdx 00000 csma r/w r/w r/w r/w r/w r/w r/w r/w bit symbol name de?ition r/w default 4.15 np next page enable 0 = no next page r/w 0 4.14 ack acknowledge 1 = auto negotiation word recognized 0 = not recognized r 0 4.13 rf remote fault 1 = auto negotiation remote fault detect 0 = no remote fault r/w 0 4.12 through 4.11 reserved r/w 0 4.10 pause pause frame capable 1 = capable of transmitting and receiving pause frames 0 = not capable r/w 0 4.9 t4 100baset4 capable 1 = capable of 100baset4 0 = not capable r/w 0 4.8 tx_fdx 100basetx full duplex capable 1 = capable of 100basetx full duplex 0 = not capable r/w 1 4.7 tx_hdx 100basetx half duplex capable 1 = capable of 100basetx half duplex 0 = not capable r/w 1 4.6 10_fdx 10basetx full duplex capable 1 = capable of 10basetx full duplex 0 = not capable r/w 1 4.5 10_hdx 10basetx half duplex capable 1 = capable of 10basetx half duplex 0 = not capable r/w 1 4.4 through 4.1 reserved r/w 0 4.0 csma csma 802.3 capable 1 = capable of 802.3 csma operation 0 = not capable r/w 1 table 13. register 4 - autonegotiation advertisement register de?ition 42 md400183/a 84225 table 14. register 5 - autonegotiation remote capability de?ition note: 5.15 bit is shifted first 5.15 5.14 5.13 5.12 5.11 5.10 5.9 5.8 np ack rf 0 0 pause t4 tx_fdx rrrrrrrr 5.7 5.6 5.5 5.4 5.3 5.2 5.1 5.0 tx_hdx 10_fdx 00000 csma rrrrrrrr bit symbol name de?ition r/w default 5.15 np next page enable 1 = next page exists 0 = no next page r0 5.14 ack acknowledge 1 = received auto negotiation word recognized 0 = not recognized r0 5.13 rf remote fault 1 = auto negotiation remote fault detect 0 = no remote fault r0 5.12 through 5.11 reserved r 0 5.10 pause pause frame capable 1 = capable of transmitting and receiving pause frames 0 = not capable r0 5.9 t4 100baset4 capable 1 = capable of 100baset4 0 = not capable r0 5.8 tx_fdx 100basetx full duplex capable 1 = capable of 100basetx full duplex 0 = not capable r0 5.7 tx_hdx 100basetx half duplex capable 1 = capable of 100basetx half duplex 0 = not capable r0 5.6 10_fdx 10basetx full duplex capable 1 = capable of 10basetx full duplex 0 = not capable r0 5.5 10_hdx 10basetx half duplex capable 1 = capable of 10basetx half duplex 0 = not capable r0 5.4 through 5.1 reserved r 0 5.0 csma csma 802.3 capable 1 = capable of 802.3 csma operation 0 = not capable r0 md400183/a 43 84225 table 15. register 16 - reserved 16.15 16.14 16.13 16.12 16.11 16.10 16.9 16.8 00000000 r/w r/w r/w r/w r/w r/w r/w r/w 16.7 16.6 16.5 16.4 16.3 16.2 16.1 16.0 01001000 r/w r/w r/w r/w r/w r/w r/w r/w bit symbol name de?ition r/w default 16.15 reserved for factory use. must be written with thru default values speci ed above for normal operation 16.0 44 md400183/a 84225 table 16. register 17 - reserved 17.15 17.14 17.13 17.12 17.11 17.10 17.9 17.8 0 0000000 r/w r/w r/w r/w r/w r/w r/w r/w 17.7 17.6 17.5 17.4 17.3 17.2 17.1 17.0 0 0000010 r/w r/w r/w r/w r/w r/w r/w r/w bit symbol name de?ition r/w default 17.15 thru 17.0 reserved for factory use. must be written with default values speci ed above for normal operation md400183/a 45 84225 table 17. register 18 - channel status output register de?ition note: 18.15 bit is shifted first 18.15 18.14 18.13 18.12 18.11 18.10 18.9 0.8 rpol dsyn_to chad1 chad0 rrrrrrrr 18.7 18.6 18.5 18.4 18.3 18.2 18.1 18.0 link_fail spd_det dplx_det cwrd ssd esd jab r r/lt r/lt r/lt r/lt r/lt r/lt r/lt bit symbol name de?ition r/w default 18.15 rpol reversed polarity detect 1 = reversed polarity detect 0 = normal r0 18.14 dsyn_to loss of synchronization detect 1 = descrambler has lost synchronization 0 = normal r0 18.13 through 18.10 reserved r 0 0 0 0 18.9 18.8 chad1 chad0 channel address 11 = accessing channel 3 10 = accessing channel 2 01 = accessing channel 1 00 = accessing channel 0 r 11/10/ 01/00 18.7 reserved r 0 18.6 link_fail link fail detect 1 = link not detected 0 = normal r/lt 1 18.5 spd_det 100/10 speed detect 1 = device in 100basetx mode 0 = device in 10 baset mode r/lt 0 18.4 dplx_det duplex detect 1 = device in full duplex mode 0 = device in half duplex mode r/lt 0 18.3 cwrd codeword error 1 = invalid 4b5b code detected on receive data 0 = normal r/lt 0 18.2 ssd start of stream error 1 = no start of stream delimiter detected on receive data 0 = normal r/lt 0 18.1 esd end of stream error 1 = no end of stream delimiter detected on receive data 0 = normal r/lt 0 18.0 jab jabber detect 1 = jabber detected 0 = normal r/lt 0 46 md400183/a 84225 table 18. register 19 - reserved 19.15 19.14 19.13 19.12 19.11 19.10 19.9 19.8 00000000 r/w r/w r/w r/w r/w r/w r/w r/w 19.7 19.6 19.5 19.4 19.3 19.2 19.1 19.0 01111111 r/w r/w r/w r/w r/w r/w r/w r/w bit symbol name de?ition r/w default 19.15 thru 19. r eserved for factory use. must be written with default values speci ed above for normal operation md400183/a 47 84225 table 19. register 20 - reserved register note: 20.15 bit is shifted first 20.15 20.14 20.13 20.12 20.11 20.10 20.9 20.8 00000000 r/w r/w r/w r/w r/w r/w r/w r/w 20.7 20.6 20.5 20.4 20.3 20.2 20.1 20.0 00000000 r/w r/w r/w r/w r/w r/w r/w r/w bit symbol name de?ition r/w default 20.15 thru 20.0 reserved for factory use. must be written to 0 for normal operation r/w 0 48 md400183/a 84225 4.0 application information 4.1 example schematics a typical example of the 84225 used for a switching hub application in twisted pair mode is shown in figure 12; an example of the 84225 used in ?er mode is shown in figure 13. 4.2 tp interface 4.2.1 transmit interface the interface between the tp outputs on tpop/n and the twisted pair cable is typically transformer coupled and terminated with the two resistors as shown in figure 12. the transformer for the transmitter is recommended to have a winding ratio of 1:1 with the center tap of the primary winding tied to vdd, as shown in figure 12. the speci?ations for such a transformer are shown in table 20. sources for quad transformers compatible with the 84225 are listed in table 21. note that both ?tacked and ?on-stacked pin out types are listed. the stacked and non-stacked designation refers to the type of rj-45 connector used on the secondary side (line side) of the transformer. the pinout of these types differ slightly so that traces to the magnetics may be kept as short and direct as possible. the "non-stacked" rj-45 (also referred to as harmonica) is a traditional horizontally oriented connector consisting of four rj-45 jacks in a single in-line assembly. the newer "stacked" connector consists of a two-over-two con?uration so that four rj-45 jacks are located in the footprint area of two side by side connectors. this is a signi?ant improvement for higher density multi-port applications and smaller system form-factors. the seeq 84225 pin-out has been optimized for connection to transformers and connectors designed for the higher density stacked con?uration. the seeq quad transceiver will also operate with non-stacked connectors using either transformers that map the pin-out to the non-stacked con?uration, or by using trace "crossovers" on the pc board layout. the transformers listed with "non-stacked" pin-outs use crossover connections inside the part to map the stacked pin-out of the 84225 to non-stacked rj-45 connectors. crossovers internal to the transformer are not made in a controlled impedance environment, so this can impact, somewhat, the cross-talk performance of the system. for best cross-talk and system performance, it is suggested that stacked connector and transformer con?urations be used. alternately, non-stacked connectors may be used with stacked transformer types and the crossover wiring can be put on the pc board using a ground plane to reduce impedance mismatch. the transmit output needs to be terminated with two external termination resistors in order to meet the output impedance and return loss requirements of ieee 802.3. it is recommended that these two external resistors be connected from vdd to each of the tpop/n outputs, and their value should be chosen to provide the correct termination impedance when looking back through the transformer from the twisted pair cable, as shown in figure 12. the value of these two external termination resistors depends on the type of cable driven by the device. refer to the cable selection section for more details on choosing the value of these resistors. to minimize common mode output noise and to aid in meeting radiated emissions requirements, it may be necessary to add a common mode choke on the transmit outputs as well as add common mode bundle termination. the transformers listed in table 21 all contain common mode chokes on both the transmit and receive sides, as shown in figure 12. common mode bundle termination is achieved by tying the unused pairs in the rj45 to chassis ground through 75 ohm resistors and a 0.01 uf capacitor, as shown in figure 12. to minimize noise pickup into the transmit path in a system or on a pcb, the loading on tpop/n should be minimized and both outputs should always be loaded equally. table 20. tp transformer speci?ation parameter speci?ation transmit receive turns ratio 1:1 ct 1:1 inductance, (uh min) 350 350 leakage inductance, (uh) 0.2 0.2 capacitance (pf max) 15 15 dc resistance (ohms max) 0.4 0.4 md400183/a 49 84225 figure 1. typical switching hub port schematic using the 84225 in twisted pair mode switch fabric quad 100/10 mb ethernet controller tpop_3 tpon_3 tpip_3 tpin_3 50 1% 50 1% 1:1 1:1 rj45 25 2 75 0.01 75 0.01 4 5 7 1 8 3 6 vdd 19 tpop_2 tpon_2 tpip_2 tpin_2 50 1% 50 1% 1:1 1:1 rj45 2 75 0.01 75 0.01 4 5 7 1 8 3 6 tpop_1 tpon_1 tpip_1 tpin_1 50 1% 50 1% 1:1 1:1 rj45 2 75 0.01 75 0.01 4 5 7 1 8 3 6 tpop_0 tpon_0 tpip_0 tpin_0 50 1% 50 1% 1:1 1:1 rj45 2 75 0.01 75 0.01 4 5 7 1 8 3 6 mdio, mdc 2 led[3:0]_[3:0] pinstrap regdef dplx[3:0] 16 system reset sd_[3:0]/ fxen__[3:0] rext 4 18 gnd clkin txclk_3 txd3_3 txd2_3 txd1_3 txd0_3 txen_3 txer_3 col_3 rxclk_3 rxd3_3 rxd2_3 rxd1_3 rxd0_3 crs_3 rxdv_3 rxer_3 txclk_2 txd3_2 txd2_2 txd1_2 txd0_2 txen_2 txer_2 col_2 rxclk_2 rxd3_2 rxd2_2 rxd1_2 rxd0_2 crs_2 rxdv_2 rxer_2 txclk_1 txd3_1 txd2_1 txd1_1 txd0_1 txen_1 txer_1 col_1 rxclk_1 rxd3_1 rxd2_1 rxd1_1 rxd0_1 crs_1 rxdv_1 rxer_1 txclk_0 txd3_0 txd2_0 txd1_0 txd0_0 txen_0 txer_0 col_0 rxclk_0 rxd3_0 rxd2_0 rxd1_0 rxd0_0 crs_0 rxdv_0 rxer_0 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 84225 10k 16 mii or 6 rmii 16 mii or 6 rmii 16 mii or 6 rmii 16 mii or 6 rmii seeq 84302 sd_thr reset speed[3:0] aneg repeater rmii_en ad_rev system clock leddef figure 12. 50 md400183/a 84225 figure 1typical switching hub port schematic using the 84225 in fiber mode switch fabric quad 100/10 mb ethernet controller fxop_3 fxon_3 fxip_3 fxin_3 3.3 v optic transceiver vdd 19 mdio, mdc 2 sd_0 rext 10k 18 gnd txclk_3 txd3_3 txd2_3 txd1_3 txd0_3 txen_3 txer_3 col_3 rxclk_3 rxd3_3 rxd2_3 rxd1_3 rxd0_3 crs_3 rxdv_3 rxer_3 txclk_2 txd3_2 txd2_2 txd1_2 txd0_2 txen_2 txer_2 col_2 rxclk_2 rxd3_2 rxd2_2 rxd1_2 rxd0_2 crs_2 rxdv_2 rxer_2 txclk_1 txd3_1 txd2_1 txd1_1 txd0_1 txen_1 txer_1 col_1 rxclk_1 rxd3_1 rxd2_1 rxd1_1 rxd0_1 crs_1 rxdv_1 rxer_1 txclk_0 txd3_0 txd2_0 txd1_0 txd0_0 txen_0 txer_0 col_0 rxclk_0 rxd3_0 rxd2_0 rxd1_0 rxd0_0 crs_0 rxdv_0 rxer_0 16 16 16 16 gen 83 gen 127 gen 83 gen 127 gen 83 gen 127 gen 70 gen 70 gen 173 gen 173 td tdb rd rdb sd fxop_3 fxon_3 fxip_3 fxin_3 3.3 v optic transceiver gen 83 gen 127 gen 83 gen 127 gen 83 gen 127 gen 70 gen 70 gen 173 gen 173 td tdb rd rdb sd vdd vdd fxop_3 fxon_3 fxip_3 fxin_3 3.3 v optic transceiver gen 83 gen 127 gen 83 gen 127 gen 83 gen 127 gen 70 gen 70 gen 173 gen 173 td tdb rd rdb sd fxop_3 fxon_3 fxip_3 fxin_3 3.3 v optic transceiver gen 83 gen 127 gen 83 gen 127 gen 83 gen 127 gen 70 gen 70 gen 173 gen 173 td tdb rd rdb sd vdd vdd 84225 sd_1 sd_2 sd_3 sd_thr pinstrap 16 system reset system clock led[3:0]_[3:0] dplx[3:0] clkin reset speed[3:0] aneg repeater rmii_en ad_rev leddef figure 13. typical switching hub port schematic using the 84225 in fx mode with 3.3v transceivers regdef md400183/a 51 84225 table 21. tp transformer sources 4.2.2 receive interface receive data is typically transformer coupled into the receive inputs on tpip/n and terminated with an external resistor as shown in figure 12. the transformer for the receiver is recommended to have a winding ration of 1:1, as shown in figure 12. the speci?ations for such a transformer are shown in table 20. sources for the transformer are listed in table 21. the receive input needs to be terminated with the correct termination impedance to meet the input impedance and return loss requirements of ieee 802.3. in addition, the receive tp inputs need to be attenuated. it is recommended that both the termination and attenuation be accomplished by placing four external resistors in series across the tpip/n inputs as shown in figure 12. the resistors should be 25%/25%/25%/25% of the total series resistance, and the total series resistance should be equal to the characteristic impedance of the cable (100 ohms for utp, 150 ohms for stp). for 100 ohm twisted pair the resistor string values should be 25 ohms each (1%). it is also recommended that a 0.1uf capacitor be placed between the center of the series resistor string and vcc in order to provide an ac ground for attenuating common mode signal at the input. this capacitor is also shown in figure 12. to minimize common mode input noise and to aid in meeting susceptibility requirements, it may be necessary to add a common mode choke on the receive input as well as add common mode bundle termination. the transformers listed in table 24 contain common mode chokes on both the transmit and receive sides, as shown in figure 12. common mode bundle termination is achieved by tying the receive secondary center tap and the unused pairs in the rj45 to chassis ground through 75 ohm resistors and a 0.01 uf capacitor, as shown in figure 12. in order to minimize noise pickup into the receive path in a system or on a pcb, the loading on tpip/n should be minimized and both inputs should be loaded equally. 4.3 tp transmit output current set the tpop/n output current level is set by an external resistor tied between rext and gnd. this output current is determined by the following equation where r is the value of rext: i out = (r/10k) * i ref where i ref = 40 ma (100 mbps, utp) = 32.6 ma (100 mbps, stp) = 100 ma (10 mbps, utp) = 81.6 ma (10 mbps, stp) for 100 ohm utp, rext should be typically set to 10k ohms and rext should be a 1% resistor in order to meet ieee 802.3 speci?d levels. once rext is set for the 100 mbps and utp modes as shown by the equation above, i ref is then automatically changed inside the device when the 10 mbps mode or utp120/stp150 modes are selected as described in the twisted pair characteristics transmit section. keep resistor rext as close to pins rext and gnd as possible in order to reduce noise pickup into the transmitter. since the tp output is a current source, capacitive and inductive loading can reduce the output voltage level from the ideal. thus, in an actual application, it might be necessary to adjust the value of the output current to compensate for external loading. the tp output level can be adjusted by changing the value of the external resistor tied to rxt. vendor part number pin out type pulse h1062 stacked bel s558- 5999b47 stacked nano pulse 6931-30 stacked valor st6179 stacked halo tg110- s453nx stacked pulse h1053 non- stacked bel s558-5999- j5 non- stacked nano pulse 6949-30 non - stacked valor st6403p non- stacked halo tg110- s456nx non- stacked 52 md400183/a 84225 4.4 transmitter droop the ieee 802.3 speci?ation has a transmitter output droop requirement for 100basetx. since the 84225 tp output is a current source, it has no perceptible droop by itself. however, the open circuit inductance of the transformer added to the device transmitter output as shown in figure 12 will cause droop to appear at the transmit interface to the tp wire. if the transformer connected to the 84225 outputs meets the requirements in table 20, the transmit interface to the tp cable will meet the ieee 802.3 droop requirements. 4.5 fiber interface 4.5.1 general the 84225 uses a pecl-type driver/receiver to achieve a thoughput of 100 mbps across a differential ?er interface. the interface comprises four signals: fxop/ fxon (output) and fxip/fxin (input). some fiber transceivers modules that will work with the 84225 are shown in table 22. the siemens fiber transceiver v23809-c8-c10 operates at 3.3v for use with the seeq 84225. 5v fiber modules such as the hp hfbr-5103 will also operate with the proper termination network described later. table 22. fiber transceiver modules vendor 3.3v 5v siemens [1] v23809-c8-c10 v23809-c8-c10 hp available hfbr-5103 soon amp contact supplier 269040-1 note 1. siemen s part operates at both 3.3v and 5v supply values. the 84225 ?er interface is enabled for each channel independently if a valid pecl fiber signal is tied to the sd_[3:0]/fxen_[3:0] pins; the ?er interface is disabled (and the tp interface enabled) by connecting the sd_[3:0]/fxen_[3:0] pins to gnd for that channel. autonegotiation and the scrambler/descrambler are disabled when the ?er interface is enabled. the voltage applied to the sd_thr pin sets the input reference level of the ?er interface for the single ended signal detect inputs only. if a 3.3 v ?er transceiver is used with the 84225, this pin should be tied to gnd. if a 5 v ?er transceiver is used, this pin needs to be tied to vcc(3.3v)-1.3 v (about 2v), but referenced to the 5v supply of the ?er transceiver. an easy way to do this is with a 15k:10k voltage divider from the 5 v supply to ground, with the center point of the divider connected to sd_thr, as shown in figure 15. 4.5.2 operation with 3.3v fiber transceivers termination on the differential outputs of the ?er transceiver module must be observed for proper impedance matching, which is normally the equivalent of 50 ohms single ended. the terminating resistor values are shown in figure 14 for fxop/fxon (outputs), fxip/ fxin (inputs) and sd_[3:0]/fxen_[3:0] (inputs) for use with 3.3v ?er modules. the calculated termination resistors on fxop/fxon are a pullup of 69.8 ohms to 3.3v and a pulldown of 174 ohms to ground. the termination network at the ?er inputs (fxip/fxin and sd_[3:0]/fxen_[3:0]) of the 84225 is speci?d by the ?er module manufacturer and will normally be a pullup of 127 ohms to 3.3v and a pulldown of 82.5 ohms to gnd, as shown in figure 14. note that the input and output termination resistor values are different since the output driver of the fiber module and the 84225 have a different structure. the interface network for 3.3v ?er transceiver modules is shown in figure 14. figure 14. fx interface to 3.3v fiber modules 4.5.3 operation with 5v fiber transceivers it is also possible to use the 84225 with 5v ?er modules by changing the resistive termination network slightly. since the 84225 fxop/fxon outputs are 5v tolerant, the output termination resistors should be a pullup of 61.9 ohms to the 5v supply, and a pulldown of 261 ohms to gnd, as shown in figure 15. this provides an ouput high voltage of 4.05v, and a low of about 3.3v to the ?er module. 3.3v seeq 84220 10/100 tx/fx transceiver vdd = 3.3v fxop fxon fxip fxin sd/fxen sd_thr 3.3v fiber transceiver vdd = 3.3v td td- rd rd- sd 127 69.8 127 82.5 82.5 174 3.3v md400183/a 53 84225 the termination network on the fxip/fxin inputs of the 84225 must be modi?d for operation with 5v modules by adding a third resistor as a ?ap on the pulldown leg, as shown in figure 15. this divides down the voltage seen at the input of the 84225 so that it does not exceed the range of the input buffer. the pullup resistor recommended by the 5v module supplier will generally remain the same - usually about 82.5 ohms to the 5v supply. the normally recommended 125 ohm pulldown resistor must be split into two. the values of this new pair should be 52.3 ohms connected to the pullup resistor and 73.2 ohms connected from the 52.3 ohm resistor to ground, providing a voltage divider function at the junction of the pair. the junction of these two resistors should be connected to the fxip/fxin and sd_[3:0]/fxen_[3:0] inputs of the 84225. this will provide a high pecl logic level of 2.36v and a low of 1.92v, which is suf?ient for operation of the 84225. an interface suitable for operation wit 5v ?er transceiver modues is shown below in figure 15. figure 15. fx interface to 5v fiber modules 4.6 mii controller interface 4.6.1 general the mii controller interface allows the 84225 to connect to any external ethernet controller without any glue logic, provided that the external ethernet controller has an mii interface that complies with ieee 802.3 as shown in figure 12 and figure 13. the 84225 also offers rmii (reduced mii) interface as a selectable option for use with controllers (macs) supporting rmii operation. by holding the rmii_en pin high, the rmii interface is enabled, cutting the required interface signals from 16 to 6. this is a signi?ant savings in board interconnect for high port count systems. for normal mii operation the rmii_en pin should be tied to gnd. refer to the rmii description in section 2 for details of the interface operation. 4.6.2 clocks standard ethernet controllers with an mii use txclk to clock data in on inputs txd[3:0]. txclk is speci?d in ieee 802.3 and on the 84225 to be an output. the 84225 requires a 25 mhz reference frequency in mii mode, and 50 mhz in rmii mode. this reference frequency must be applied to the clkin pin. clkin generates txclk inside the 84225; thus, data can be clocked into the 84225 on the rising edge of output clock txclk or on the rising edge of input clock clkin. if a nonstandard controller is used to interface to the 84225, or in repeater applications, there may be a need to clock txd[3:0] into the 84225 on the rising edge clkin. where clkin is used as the input clock, txclk can be left open or used for another purpose. 4.6.3 mii disable the mii outputs can be placed in the high impedance state and inputs disabled by setting the mii disable bit in the mi serial port control register. when this bit is set to the disable state, the tp and fx outputs are both disabled and transmission is inhibited. the default value of this bit when the device powers up or is reset is dependent on the device address. if the device address latched into phyad[4:0] at reset is 11111, it is assumed that the device is being used in applications where there maybe more than one device sharing the mii bus, like external phy s or adapter cards, so the device powers up with the mii interface disabled. if the device address latched into phyad[4:0] at reset is not 11111, it is assumed that the device is being used in an application where it is the only device on the mii bus, like hubs, so the device powers up with the mii interface enabled. 4.7 fbi controller interface the fbi (five bit interface) controller interface has the same characteristics of the mii except that the data path is ?e bits wide, instead of 4 bits wide per the mii. the ?e bit wide data path is automatically enabled when the 4b5b encoder is bypassed. because of this encoder/ decoder bypass, the fbi is used primarily for repeaters or 3.3v seeq 84220 10/100 tx/fx transceiver vdd = 3.3v fxop fxon fxip fxin sd/fxen sd_thr 5v fiber transceiver vdd = 5v td td- rd rd- sd 82.5 15k 10k 73.2 61.9 261 vdd = 5v 52.3 82.5 52.3 73.2 54 md400183/a 84225 other applications where the phy encoding/decoding function is not needed. for more details about the fbi, see the non-mii based repeaters section. 4.8 repeater applications 4.8.1 mii based repeaters the 84225 can be used as the physical interface for mii based repeaters by using the standard mii/rmii as the interface to the repeater core. for most repeaters, it is necessary to disable the internal crs loopback. this can be done by asserting the repeater input of the chip. for some particular types of repeaters, it may be desirable to either enable or disable autonegotiation, force half duplex operation, and enable either 100 mbps or 10 mbps operation. all of these modes can be con?ured by either asserting the appropriate hardware pins or by setting the appropriate bits in the mi serial port control register. 4.8.2 clocks normally, transmit data sent over the mii/rmii/fbi is clocked into the 84225 by the rising edge of the output clock txclk. it may be desireable or necessary in some repeater applications to clock in transmit data from a master clock from the repeater core. this would require that transmit data be clocked in on the edge of an input clock. an input clock is available for clocking in data on txd by the rising edge on the clkin pin. notice from the timing diagrams that clkin generates txclk, and txd data is clocked in on txclk edges. this means that txd data is also clocked in on the clkin edge as well. thus, an external clock driving the clkin input can also be used as the clock for txd. 4.9 serial port 4.9.1 general the 84225 has a mi serial port to set all of the devices's con?uration inputs and read out the status outputs. any external device that has an ieee 802.3 compliant mi interface can connect directly to the 84225 without any glue logic, as shown in figure 12 and figure 13. as described earlier, the mi serial port consists of ?e lines: mdc, mdio, and phyad[4:2]. however, only 2 lines, mdc and mdio, are needed to shift data in and out. phyad[4:2] de?e the three most signi?ant bits of the phy address, as described in the section 4.9.3, serial port addressing section. 4.9.2 polling vs. interrupt the status output bits can be monitored by either polling the serial port or with the interrupt output. if polling is used, the registers can be read at regular intervals and the status bits can be checked against their previous values to determine any changes. to make polling simpler, all the registers can be accessed in a single read or write cycle by setting the register address bits regad[4:0] to 11111 and adding enough clocks to read out all the bits, provided the multiple register access feature has been enabled. 4.9.3 serial port addressing the device address for the mi serial port is selected by connecting the phyad[4:2] pins to the desired value. the phyad[1:0] addresses are internally hardwired for each channel as shown in both tables 5 and 7. 4.10 unmanaged port configuration the 84225 has con?uration inputs which can ?ver-ride the default con?uration state obtained on power-up or reset of the device. use of these pins aneg, speed_[3:0], and dplx_[3:0] allow selection of global autonegotiation, individual port speed (10/100), and individual port duplex (full/half), by properly strapping these pins to vdd or vss as shown in table 23. note that these pins should not float, but must be connected either high or low for proper operation. in order to obtain the ?efault mode of operation? ie: auto-negotiation enabled, 100mbs, and half duplex; the aneg, speed_[3:0], and dplx_[3:0] pins should be set to 1,1,0 respectively. md400183/a 55 84225 table 23. hardware con?uration 4.13 long cable ieee 802.3 speci?s that 10baset and 100basetx operate over twisted pair cable lengths from 0 to 100 meters. the squelch levels can be reduced by 4.5 db if the receive level adjust bit is appropriately set in the mi serial port channel con?uration register, which will allow the 84225 to operate with up to 150 meters of twisted pair cable. the equalizer is already designed to accomodate between 0 to 150 meters of cable. 4.14 clock the 84225 requires a 25 mhz reference frequency for internal signal generation in mii mode, and 50 mhz in rmii mode. the appropriate reference frequency must be applied to the clkin pin. 4.15 led drivers the led[3:0] outputs can all drive led s tied to vdd as shown in figure 12 and figure 13. in addition, the led[3:0] outputs can drive led s tied to gnd as well. the led de?itions assume that the led outputs are tied to vdd, active low signals (otherwise the led outputs will indicate their respective opposite events.) the leddef pin determines the default settings for led[3:0]. if leddef = 0, the default functions for led[3:0] are link 100, activity, full duplex, and link 10, respectively. if leddef = 1, the led functions for led[3:0] are forced to link + activity, collision, full duplex and 10/100 mbps operation, respectively. table 5 de?es the led functions. table 4 de?es the led events. the led[3:0] outputs can also drive other digital inputs. thus, led[3:0] can also be used as digital outputs whose function can be user de?ed and controlled through the mi serial port.5v compatible i/o operation. 4.16 5v compatible i/o operation the input and output pins of the 84225 are tolerant of signal levels up to a maximum of 5.5v (including overshoot etc.). this allows the transceiver to be operated with 5v controllers that have ttl i/o characteristics (0.8 to 2.0v input levels) without the use of levelshifters or other interfaces. controllers and other system components may be operate with 5v supplies and all inter-chip signals may be connected directly to the 84225. all required external logic levels must retain ttl compatability since the 84225 outputs are not guaranteed to achieve higher than 2.3v with a load of 10ma. however, the inputs of the 84225 will tolearte ttl or cmos logic levels being driven into the device. this should make replacement of the physical layer transceivers in existing designs quite simple since any 5v devices do not need to be changed. 4.17 power supply decoupling there are 18 vdd's and 19 gnd's on the 84225. all vdd's on each individual side should be connected together (grouped) and tied to a power plane, as close as possible to the 84225 supply pins. if the vdd's vary in potential by even a small amount, noise and latchup can result. the 84225 vdd pins should be kept to within 50 mv of each other. all gnd's should be connected as close as possible to the device with a large ground plane. if the gnd's vary in potential by even a small amount, noise and latchup can result. the gnd pins should be kept to within 50 mv of each other. a 0.01-0.1uf decoupling capacitor should be connected between the vdd group and gnd on each of the 4 sides of the 84225 as close as possible to the device pins, preferably within 0.5 in. the value should be chosen depending on whether the noise from vdd-gnd is high or low frequency. a conservative approach would be to con?uration state auto- negotiate speed duplex normal (poc/reset) enabled advertise 10/100 advertise full/half con? pins aneg=1 speed_ [3:0]=1 dplx_ [3:0]=0 complement state disabled 10mbs full con? pins aneg=0 speed_ [3:0]=0 dplx_ [3:0]=1 56 md400183/a 84225 use two decoupling capacitors on each side, one 0.1uf for low frequencys, and one 0.001 uf for high frequency noise on the power supply. the vdd connection to the transmit transformer center tap shown in figures 12 and 13 must be well decoupled in order to minimize common mode noise injection from the supply into the twisted pair cable. it is recommended that a 0.01 uf decoupling capacitor be placed between the transformer center tap vdd connection and the 84225 gnd plane. this decoupling capacitor should be physically placed as close as possible to the transformer center tap, preferably within 0.5 in. the pcb layout and power supply decoupling discussed above should provide suf?ient decoupling to achieve the following when measured at the device: (1) the resultant ac noise voltage measured across each vdd/gnd set should be less than 100 mvpp, (2) all vdd s should be within 50 mvpp of each other, and (3) all gnd s should be within 50 mvpp of each other. md400183/a 57 84225 5.0 specifications 5.1 absolute maximum ratings absolute maximum ratings are limits beyond which may cause permanent damage to the device or affect device reliability. all voltages are speci?d with respect to gnd, unless otherwise speci?d. v dd supply voltage ........................................................................................................................... -0.3v to +4.0v all inputs and outputs .......................................................................................................................... -0.3v to 5.5v package power dissipation ........................................................................................................... 3.0 watt @ 70 o c storage temperature ......................................................................................................................... -65 to +150 o c temperature under bias...................................................................................................................... -10 to +80 o c lead temperature (soldering, 10 sec).......................................................................................................... 260 o c body temperature (soldering, 30 sec) ......................................................................................................... 220 o c note that all inputs and outputs are 5v tolerant 5.2 dc electrical characteristics unless otherwise noted, all test conditions are as follows: 1. t a = 0 to +70 o c 2. v dd = 3.3v + 5% 3. 25 mhz + 0.01% 4. rext = 10k + 1%, no load limit sym parameter min typ max unit conditions v il input low voltage 0.8 volt v ih input high voltage 2 volt i il input low current ? ua vin = gnd all except reset 10 50 ua vin = gnd reset i ih input high current ? ua vin = vdd v ol output low voltage 0.4 volt iol = -4 ma, except led[3:0] 1 volt iol = -20 ma, led[3:0] v oh output high voltage vdd -1.0 volt ioh = 4 ma all except led[3:0] vdd -1.0 volt ioh = 10 ma, led[3:0] 2.4 volt ioh = 10 ua c in input capacitance 5pf i dd vdd supply current 450 ma transmitting 100%, 100 mbps 450 ma transmitting 100%, 10 mbps i gnd gnd supply current 700 ma transmitting 100%, 100 mbps, note 1 700 ma transmitting 100%, 10 mbps, note 1 200 ua powerdown note 1. ignd includes current ?wing into gnd from the external resistors and transformer on tpop/ tpon as shown in figure 12. 58 md400183/a 84225 twisted pair characteristics, transmit unless otherwise noted, all test conditions are as follows: 1. t a = 0 to +70 o c 2. v dd = 3.3 v + 5% 3. 25 mhz + 0.01% 4. rext=10k + 1%, no load 5. tpop/n loading shown in figure 12 or equivalent limit sym parameter min typ max unit conditions t ov tp differential output voltage 0.950 1.000 1.050 v pk 100 mbps, utp mode, 100 ohm load 1.165 1.225 1.285 v pk 100 mbps, stp mode, 150 ohm load 2.2 2.5 2.8 v pk 10 mbps, utp mode, 100 ohm load 2.694 3.062 3.429 v pk 10 mbps, stp mode, 150 ohm load t ovs tp differential output voltage symmetry 98 102 % 100 mbps, ratio of positive and negative amplitude peaks on tpop/n t orf tp differential output rise and fall time 3.0 5.0 ns 100 mbps t orfs tp differential output rise and fall time symmetry + 0.5 ns 100 mbps, difference between rise and fall times on tpop/n t odc tp differential output duty cycle distortion + 0.25 ns 100 mbps, output data=0101... nrzi pattern unscrambled, measure at 50% points t oj tp differential output jitter + 0.7 ns 100 mbps, output data=scrambled /h/ t oo tp differential output overshoot 5.0 % 100 mbps t ovt tp differential output voltage template see figure 4 10 mbps t soi tp differential output soi voltage template see figure 6 10 mbps t lpt tp differential output link pulse voltage template see figure 7 10 mbps, nlp and flp t oiv tp differential output idle voltage 50 mv 10 mbps, measured on secondary side of xfmr in figure 12 t oia tp output current 38 40 42 ma pk 100 mbps, utp with tlvl[3:0]=1000 31.06 32.66 34.26 ma pk 100 mbps, stp with tlvl[3:0]=1000 88 100 112 ma pk 10 mbps, utp with tlvl[3:0]=1000 71.86 81.64 91.44 ma pk 10 mbps, stp with tlvl[3:0]=1000 t oir tp output current adjustment range 0.80 1.2 adjustable with rext, relative to t oia with rext=10k 0.86 1.16 adjustable with tlvl[3:0]. see section 4.3. relative to value at tlvl[3:0]=1000. t ora tp output current tlvl step accuracy + 50 % relative to ideal values in table 2. values relative to output with tlvl[3:0]=1000. t or tp output resistance 10k ohm t oc tp output capacitance 15 pf md400183/a 59 84225 twisted pair characteristics, receive unless otherwise noted, all test conditions are as follows: 1. ta= 0 to +70? 2. vdd = 3.3v +5% 3. 25 mhz +0.01% 4. rext = 10k +1%, no load 5. 62.5/10 mhz square wave on tp inputs in 100/10 mbps limit sym parameter min typ max unit conditions r st tp input squelch threshold 166 500 mv pk 100 mbps, rlvl=0 310 540 mv pk 10 mbps, rlvl=0 60 200 mv pk 100 mbps, rlvl=1 217 378 mv pk 10 mbps, rlvl=1 r ut tp input unsquelch threshold 100 300 mv pk 100 mbps, rlvl=0 186 324 mv pk 10 mbps, rlvl=0 60 180 mv pk 100 mbps, rlvl=1 130 227 mv pk 10 mbps, rlvl=1 r ocv tp input open circuit voltage v dd - 2.4 ?0.2 volt voltage on either tpip or tpin with respect to gnd r cmr tp input common mode voltage range r ocv ?.25 volt voltage on either tpip or tpip with respect to gnd r dr tp input differential voltage range v dd volt r ir tp input resistance 5k ohm r ic tp input capacitance 10 pf 60 md400183/a 84225 fiber interface characteristics, transmit and receive unless otherwise noted, all test conditions are as follows: 1. ta= 0 to +70? 2. vdd = 3.3v?% 3. 25 mhz ?.01% 4. rext = 10k ?%, no load 5. fxop/n loading shown in figure 13 or equivalent limit sym parameter min typ max unit conditions f ovh fiber output level, high v dd - 1.020 v dd - 0.880 volt single ended fxop/n relative to gnd f ovl fiber output level, low v dd - 1.810 v dd - 1.620 volt single ended fxop/n relative to gnd f div fiber diffferential input voltage 0.150 volt fxip/n f cmr fiber input common mode voltage range 1.35 v dd -0.8 volt fxip/n f sdih sd/fxen input high v sd_thr v this spec applies when device voltage - 50 mv is connected to 5 v external ?er optic transceivers. v sd_thr is the voltage applied to the sd_thr pin and is spec?d by f sdthr . vcc - v this spec applies when device 1.165 is connected to 3.3v external ?er optic transceivers. sd_thr is tied to gnd. f sdil sd/fxen input low v sd_thr v this spec applies when device voltage +50 mv is connected to 5v external ?er optic transceivers. v sd_thr is the voltage applied to the sd_thr pin and is spec?d by f sdthr . vcc- this spec applies when device 1.475 is connected to 3.3v external ?er optic transceivers. sd_thr is tied to gnd. f sdthr sd_thr input voltage vcc vcc vcc v this spec applies when device -1.3 v 1.3 v -1.3 v is connected to 5v external -10% +10% ?er optic transceivers. when interfacing to 3.3v ?er optic transceivers, sd_thr is tied to gnd. f dis fiber interface disable voltage, sd/fxen pin 0.45 0.85 volt for disabling fiber interface f lv l internal/external signal detect level select, sd_thr pin 0.45 0.85 volt for selecting interface to either 3.3v or 5 v external fiber transceivers md400183/a 61 84225 ac test timing conditions unless otherwise noted, all test conditions are as follows: 1. t a = 0 to +70 o c 2. v dd = 3.3 v + 5% 3. 25 mhz + 0.01% 4. rext = 10k + 1%, no load 5. input conditions: all inputs: tr,tf <= 10 ns, 20-80% 6. output loading tpop/n: same as figure 12 or equivalent, 10 pf regdef: 1k pullup, 50 pf all other digital outputs: 25 pf 7. measurement points: tpop/n, tpip/n: 0 v during data, + 0.3 v at start/end of packet all other inputs and outputs: 1.4 v 5.7 clock timing characteristics refer to figure 16 for timing diagram limit sym parameter min typ max unit conditions t 1 clkin period 39.996 40 40.004 ns mii 19.996 20 20.002 ns rmii t 2 clkin high time 16 ns mii 7 ns rmii t 3 clkin low time 16 ns mii 7 ns rmii t 4 clkin to txclk delay 10 ns 100 mbps, mii 20 ns 10 mbps, mii txclk (100 mb) txclk (10 mb) t 4 t 4 t 4 clkin t 1 t 2 t 3 figure 16. output timing 62 md400183/a 84225 transmit timing characteristics refer to figures 17-18 for timing diagram limit sym parameter min typ max unit conditions t 11 txclk period 39.996 40 40.004 ns 100 mbps 399.96 400 400.04 ns 10 mbps t 12 txclk low time 16 20 24 ns 100 mbps 160 200 240 ns 10 mbps t 13 txclk high time 16 20 24 ns 100 mbps 160 200 240 ns 10 mbps t 14 txclk rise/fall time 10 ns t 15 txen setup time 15 4 ns ns mii rmii t 16 txen hold time 0 2 ns ns mii rmii t 17 crs during transmit assert time 40 ns 100 mbps, mii and fbi 400 ns 10 mbps, mii and fbi t 18 crs during transmit deassert time 160 ns 100 mbps 900 ns 10 mbps t 19 txd setup time 15 ns mii 4 rmii t 20 txd hold time 0ns mii 2 rmii t 21 txer setup time 15 ns t 22 txer hold time 0ns mii 2 rmii t 23 transmit propagation delay 60 140 ns 100 mbps, mii 140 ns 100 mbps, fbi 600 ns 10 mbps t 24 transmit output jitter + 0.7 ns pk-pk 100 mbps + 5.5 ns pk-pk 10 mbps t 25 transmit soi pulse width to 0.3v 250 ns 10 mbps t 26 transmit soi pulse width to 40 mv 4500 ns 10 mbps t 27 ledn delay time 25 ms ledn programmed for activity t 28 ledn pulse width 80 105 ms ledn programmed for activity md400183/a 63 84225 figure 17. transmit timing - 100 mbps rmii 100 mbps same as mii 100 mbps except: 1. data input on txd[1:0]; txd[3:2] not used. 2. all timing referenced to clkin instead of txclk fbi 100 mbps same as mii 100 mbps except: 1. txer converted to txd4. 2. rxer converted to rxd4. mii 100 mbps txclk txen crs txd [3:0] t 11 ledn txer t 13 t 14 t 14 t 18 t 16 t 15 t 17 t 27 t 28 t 12 n0 n3 n2 n1 19 tt 20 t 23 tpo /j/k/ idle idle data /t/r/ idle t 21 t 22 t 24 64 md400183/a 84225 figure 18. transmit timing - 10 mbps mii 10 mbps rmii 10 mbps same as, mii 10 mbps except : 1. data input on txd [1:0]; txd[3:2] not used. 2. all timing referenced to clkin instead of txclk. 3. each data di-bit on txd [1:0] is present for 10 consecutive clkin cycles. txclk txen crs txd [3:0] t 11 ledn tpo t 13 t 14 t 14 t 18 t 16 t 15 t 17 n0 n3 n2 n1 t 27 t 23 t 28 soi t 24 19 tt 20 t 12 t 26 t 25 preamble preamble data data md400183/a 65 84225 receive timing characteristics refer to figures 19-22 for timing diagram limit sym parameter min typ max unit conditions t 31 start of packet to 200 ns 100 mbps, mii 200 ns 100 mbps, rmii 700 ns 10 mbps t 32 end of packet to crs 130 240 ns 100 mbps, mii 280 ns 100 mbps rmii 600 ns 10 mbps, mii. relative to start of soi pulse 1000 ns 10 mbps, rmii. relative to start of soi pulse t 33 start of packet to 240 ns 100 mbps 3600 ns 10 mbps t 34 end of packet to 280 ns 100 mbps, mii 360 ns 100 mbps, rmii 1000 ns 10 mbps, mii. relative to start of soi pulse 2800 ns 10 mbps, rmii. relative to start of soi pulse t 37 rxclk to rxdv -8 8 ns 100 mbps, mii -4 2 ns 100 mbps and 10 mbps, rmii -80 80 ns 10 mbps, mii t 38 rxclk high time 18 20 22 ns 100 mbps 180 200 600 ns 10 mbps t 39 rxclk low time 18 20 22 ns 100 mbps 180 200 600 ns 10 mbps t 40 soi pulse minimum 125 200 ns 10 mbps width required for idle detection measured tpip/n from last zero cross to 0.3 v point. t 41 receive input jitter ?.0 ns pk-pk 100 mbps ?3.5 ns pk-pk 10 mbps t 43 ledn delay time 25 ms ledn programmed for activity t 44 ledn pulse width 60 105 ms ledn programmed for activity t 45 rxclk, rxd, crs, 10 ns rxdv, rxer output rise and fall times crs assert delay deassert delay rxdv assert delay rxdv deassert delay rxd, rxer delay 66 md400183/a 84225 figure 19. receive timing, start of packet - 100 mbps, mii & fbi fbi 100 mbps same as mii 100 mbps except: 1. rxer converted to rxd4. 2. txer converted to txd4. mii 100 mbps rxd [3:0] pledn t 31 t 44 tpi data data data data data crs rxclk tx tx tx tx tx t 33 rxdv t 38 t 39 preamble preamble t 37 rxer t 37 t 37 t 43 rx rx rx rx rx rx t 37 data data data data data data data data data data data data idle k j data t 41 preamble preamble preamble md400183/a 67 84225 figure 19a. receive timing, start of packet - 100 mbps, rmii rxd [1:0] t 31 tpi data data data data data crs clkin tx tx tx tx tx t 33 rxdv t 38 t 39 preamble preamble t 37 rxer t 37 rx rx rx rx rx rx t 37 data data data data data data data data data data data data idle k j data t 41 preamble preamble preamble t 37 rmii 100 mbps 68 md400183/a 84225 figure 20. receive timing, end of packet - 100 mbps mii 100 mbps fbi 100 mbps same as mii 100 mbps except: 1. txer converted to rxd4. 2. rxer converted to txd4. t 32 tpi crs rxclk t 37 t 34 rxdv t 38 rxd [3:0] t 39 data data data data data data data rx rx rx rx rx rx rx rx tx tx data r t riiiiii iiiii i i iiii i i rmii 100 mbps t 32 tpi crs clkin t 38 rxd [1:0] t 39 data data data data data data data rx rx rx rx rx rx rx rx tx tx data r t riiii iiii ii ii i iiii i i t 34 t 37 t 37 md400183/a 69 84225 figure 21. receive timing, start of packet - 10 mbps, mii mii 10 mbps rxd [3:0] ledn t 31 t 44 crs rxclk tx tx tx tx tx rx rx rx rx rx rx t 37 t 33 rxdv t 38 t 39 preamble preamble data data t 37 rxer t 43 tpi data data t 41 data 70 md400183/a 84225 figure 21a. receive timing, start of packet - 10 mbps, rmii rxd [1:0] ledn t 31 t 44 crs clkin tx tx tx tx tx rx rx rx rx rx rx t 38 t 39 preamble preamble data data t 37 rxer t 43 tpi data data t 41 data t 33 note 1 data rmii 10 mbps note 1: each di-bit is present on rxd[1:0] for 10 consecutive clkin cycles. md400183/a 71 84225 figure 22. receive timing, end of packet - 10 mbps, mii mii 100 mbps t 32 tpi crs rxclk rx rx rx t 37 t 34 rxdv t 38 t 39 rx rx rx rx rx tx tx rxd [3:0] data data data data data data data data data data data data t 40 soi t 41 72 md400183/a 84225 figure 22a. receive timing, end of packet - 10 mbps, rmii rmii 10 mbps t 32 crs clkin rx rx rx t 38 t 39 rx rx rx rx rx tx tx rxd [3:0] data data data data data data data tpi data data data data data t 40 soi t 41 t 34 t 37 md400183/a 73 84225 collision timing characteristics refer to figures 23-25 for timing diagram limit sym parameter min typ max unit conditions t 51 rcv packet start to col assert time 200 ns 100 mbps 700 ns 10 mbps t 52 rcv packet stop to col deassert time 130 240 ns 100 mbps 300 ns 10 mbps t 53 xmt packet start to col assert time 200 ns 100 mbps 700 ns 10 mbps t 54 xmt packet stop to col deassert time 240 ns 100 mbps 300 ns 10 mbps t 55 ledn delay time 25 ms ledn programmed for collision t 56 ledn pulse width 80 105 ms ledn programmed for collision t 57 collision test assert time 5120 ns t 58 collision test deassert time 40 ns 800 ns 10 mbps t 60 col rise and fall time 10 ns 74 md400183/a 84225 t 32 tpi crs rxclk rx rx rx t 37 t 34 rxdv t 38 t 39 rx rx rx rx rx tx tx rxd [3:0] data data data data data data data data data data data data t 40 soi t 41 t 55 col tpi tpo ledn t 51 t 52 t 56 figure 23. collision timing, receive mii 100 mbps fbi 100 mbps same as mii 100 mbps mii 100 mbps md400183/a 75 84225 t 55 col tpi i tpo i data data data data data data data data data data data i k j i i data i i r t data ledn data data data data t 51 t 52 t 56 t 55 col tpi tpo ledn t 51 t 52 t 56 figure 24. collision timing, transmit fbi 100 mbps same as mii 100 mbps mii 100 mbps mii 100 mbps 76 md400183/a 84225 txen mii 100mb col t 58 57 t figure 25. collision test timing md400183/a 77 84225 link pulse timing characteristics refer to figures 26-27 for timing diagram limit sym parameter min typ max unit condition t 61 nlp transmit link pulse width see figure 8 ns t 62 nlp transmit link pulse period 824ms t 63 nlp receive link pulse width required for detection 50 ns t 64 nlp receive link pulse minimum period required for detection 67ms link_test_min t 65 nlp receive link pulse maximum period required for detection 50 150 ms link_test_max link_loss t 66 nlp receive link pulses required to exit link fail state 3 3 3 link pulses lc_max t 67 flp transmit link pulse width 100 150 ns t 68 flp transmit clock pulse to data pulse period 55.5 62.5 69.5 us interval_timer t 69 flp transmit clock pulse to clock pulse period 111 125 139 us t 70 flp transmit link pulse burst period 822ms transmit_link_burst_timer t 71 flp receive link pulse width required for detection 50 ns t 72 flp receive link pulse minimum period required for clock pulse detection 525us ?_test_min_timer t 73 flp receive link pulse maximum period required for clock pulse detection 165 185 us ?_test_max_timer t 74 flp receive link pulse minimum period required for data pulse detection 15 47 us data_detect_min_timer 78 md400183/a 84225 link pulse timing characteristics (continued) refer to figures 26-27 for timing diagram limit sym parameter min typ max unit condition t 75 flp receive link pulse maximum period required for data pulse detection 78 100 us data_detect_max_timer t 76 flp receive link pulses required to detect valid flp burst 17 17 link pulses t 77 flp receive link pulse burst minimum period required for detection 57ms nlp_test_min_timer t 78 flp receive link pulse burst maximum period required for detection 50 150 ms nlp_test_max_timer t 79 flp receive link pulses bursts required to detect autonegotiation capabil- ity 3 3 3 link pulse bursts t 80 flp receive acknowl- edge fail period 1200 1500 ms t 81 flp transmit renegoti- ate link fail period 1200 1500 ms break_link_timer t 82 nlp receive link pulse maximum period required for detection after flp negotation has completed 750 1000 ms link_fail_inhibit_timer md400183/a 79 84225 figure 26. nlp link pulse timing tpo t 61 a.) transmit nlp t 62 tpi t 63 b.) receive nlp t 64 pledn t 66 t 65 80 md400183/a 84225 figure 27. flp link pulse timing tpo t 67 a.) transmit flp and transmit flp burst t 68 tpi t 71 b.) receive flp t 73 tpi clk data clk data data clk clk t 70 clk data data clk t 72 31.25 62.5 93.75 125 156.25 t 74 t 75 c.) receive flp burst ledn t 77 t 78 t 79 t 69 md400183/a 81 84225 jabber timing characteristics refer to figure 28 for timing diagram limit sym parameter min typ max unit conditions t 91 jabber activation delay time 50 100 ms 10 mbps t 92 jabber deactivation delay time 250 750 ms 10 mbps figure 28. jabber timing tpo txen col 91 t crs 91 t 91 t 92 t mii 100 mbps fbi 100 mbps mii 10 mbps not applicable not applicable 82 md400183/a 84225 led driver timing characteristics refer to figure 29 for timing diagram limit sym parameter min typ max unit conditions t 96 led[3:0] on time 80 105 ms led[3:0] programmed to blink t 97 led[3:0] off time 80 105 ms led[3:0] programmed to blink led[5:0] t 96 t 97 figure 29. led driver timing md400183/a 83 84225 mi serial port timing characteristics refer to figure 30 for timing diagram limit sym parameter min typ max unit conditions t 101 mdc high time 20 ns t 102 mdc low time 20 ns t 103 mdio setup time 10 ns write bits t 104 mdio hold time 10 ns write bits t 105 mdc to mdio delay 20 ns read bits t 106 mdio hi-z to active delay 20 ns write-read bit transition t 107 mdio active to hi-z delay 20 ns read-write bit transition t 108 frame delimiter (idle) 32 clocks # of consecutive mdc clocks with mdio = 1 t 110 mdc to mdio interrupt pulse assert delay 100 ns t 111 mdc to mdio interrupt pulse deassert delay 100 ns figure 30. mi serial port timing mdio (read) t 101 mdc mdio (write) 013 114 15 30 17 16 31 t 102 d15 d0 d14 ta0 t 105 t 107 t 106 103 t 104 t regad0 st1 st0 ta0 ta1 d15 d1 d0 st0 st1 regad0 103 t 104 t ta1 84 md400183/a 84225 ordering information q package type temperature range part type q ?0 c to +70 c quad 100 base-tx/fx10 base-t physical layer device (phy) 84225 q q = plastic quad flat pack z / product rev revision history march 2, 1999: md400183/?has been changed to md400183/a global: references to jam has been changed to ad_rev, and mdint has been changed to regdef. march 2, 1999 page 6, pin description - pin #98, row has been completely changed. page 7, pin description - pin #110, i/o, i pulldown has been changed to i. page 8, pin description - pin #101, pin name rmii_en has been changed to rmii_en. page 11, block diagram - references to jam and mdint have been change to ad_rev and regdef, respectively. page 33, 2.25.7 invalid registers - section 2.25.7 invalid registers is new. page 35, table 7. mi serial port structure - symbol regad4[4:0] de?ition, copy, ...if regdef pin asserted and... has been deleted. page 36 table 8. mi serial port register map - bit x.7, 18 channel status output, int has been changed to 0. - bit x.10, 4 autonegot. advertisement, 0 has been changed to pause. - bit x.10, 5 autonegot. remote capability, 0 has been changed to pause. this document is subject to changed without notice. seeq technology incorporated assumes no responsibility for any errors contained herein. copyright by seeq technology incorporated, all rights reserved. md400183/a 85 84225 revision history page 41, table 15 register 4 - autonegotiation advertisement register de?ition - bit 4.10 has been changed from 0 to pause. - row 4.10 has been added. page 42, table 16 register 5 - autonegotiation remote capability de?ition - bit 5.10 has been changed from 0 to pause. - row 5.10 has been added. page 45, table 17 register 18 - channel status output register de?ition - bit 18.7, is now blank. - row bit 18.7, symbol is now blank, name is now blank, de?ition has been changed to reserved. page 49, figure 12. typical switching hub port schematic using the 84225 in twisted pair mode - references to jam and mdint have been changed to ad_rev and regdef, respectively. page 50, figure 13. typical switching hub port schematic using the 84225 in fx mode with 3.3v transceivers - references to jam and mdint have been changed to ad_rev and regdef, respectively. page 73, collision characteristics - any references to jam have been deleted. - row t 59 has been deleted. page 77, figure 26. jam timing - figure 26 jam timing has been deleted. page 79, figure 26. nlp link pulse timing - figure 26. nlp link pulse timing is new. 86 md400183/a 84225 31.20 ?0.30 28.00 ?0.20 31.20 ?0.30 28.00 ?0.20 1.325 ref. 0.30 ?0.10 0.65 ref. 0.25 min. 0.18 ?0.05 0.10 max #1 208 pqfp see detail a 0 - 8 0.88 ?0.15 detail a 3.40 ?0.20 4.10 max. #160 1. all dimensions are in (millimeters). qq84220 160 pin mqfp technology incorporated qq84225 |
Price & Availability of 84225
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |